RFChipAgent: Multi-Agentic AI Flow for Analog/RF Chip Design

arXiv:2610.10858 · cs.AR, cs.AI, cs.LG, cs.MA, cs.SY, eess.SY · Submitted 2026-10-07 · Read on arXiv

Listen

Radio episode about this paper

Transcript

Introduction to the show: ident: AI Radio. Generated commentary on the latest Artificial Intelligence papers.

Tom: Today's paper: "RFChipAgent: Multi-Agentic AI Flow for Analog/RF Chip Design".

Jane: The gist: This work introduces RFChipAgent, a first-of-its-kind multi-agentic AI flow for end-to-end design automation of Analog/RF circuits, which autonomously orchestrates the complete design flow under human supervision.

Tom: First, who's behind it and why it matters.

Paper summary: Tom: We've been looking at the RFChipAgent paper, this whole multi-agent system built for designing analog or RF chips from start to finish automatically but with a human in the loop.

Jane: Yeah, it’s a complex setup involving various AI components that work together to design a circuit entirely on its own under some kind of human oversight.

Lu: What’s really interesting here is how they structured this whole system around four key parts: knowledge gathering, then picking the best topology based on what they found, and finally generating the schematic and testbench with simulation feedback.

Meng: From an engineering point of view, the real win seems to be how it uses that feedback loop—the trust-scored database—to actually improve design choices instead of just letting the AI guess randomly.

Lalam: I think this shows you can move past one massive AI and build a bunch of specialized agents where each one focuses on a specific part of the design process, like matching or sizing.

Tom: It’s about replacing that old way we did things, the trial and error method, with something more systematic, almost like having an automated design team working together.

Jane: And they manage to do this by using existing engineering documents to pull in relevant knowledge before the actual design process even begins.

Lu: The authors put a lot of focus on making sure that pulling in knowledge isn't just random searching; they use specific indexing methods to track exactly where every piece of information came from, which helps with accuracy.

Meng: That level of tracking is crucial for me because if something goes wrong in the design later, I need to know precisely why the AI chose that particular path.

Lalam: Exactly, and having that structured approach means it’s less likely to just make up a solution for a complex RF circuit when it doesn't actually exist.

Tom: So, what does this mean for designers who aren't super deep into the AI stuff? Does this actually speed things up in practice when they are working on real projects?

Jane: The results they show with that wideband LNA example suggest it can cut down the amount of effort needed to get a design that is verified by a lot.

Lu: They used specific metrics, like noise performance and power budgets, to steer the topology agent, which is much smarter than just letting it pick anything randomly.

Meng: The validation process they employ—checking physical validity gates before every simulation step—that’s what tells me this isn't just theoretical; it’s built for real-world constraints.

Lalam: It means the AI isn't just drawing schematics; it’s optimizing for actual performance metrics like S11 and noise figure inside a simulator-in-the-loop environment.

Tom: Looking at the whole paper, the main thing is that we are moving toward exploring design spaces where the AI actively learns from its mistakes to find better solutions more quickly.

Jane: It shifts what a designer does away from doing all of that heavy iterative work and instead focusing on setting those high-level performance targets for these agents.

Lu: The authors are creating a framework that mixes using different types of knowledge retrieval with sequential, specialized agents to handle really tough design challenges autonomously.

Meng: This could really cut down the time spent on initial concept generation and figuring out layout options for new RF architectures.

Lalam: And I see this improving the whole culture of design by making complex optimization accessible through these structured, agentic workflows we can use.

Conclusion: Tom: So we're wrapping up our look at RFChipAgent: Multi-Agentic AI Flow for Analog/RF Chip Design, and we're talking about what this whole setup means for the field right now.

Jane: This system introduces several autonomous agents that work together to handle the entire design flow of an analog or RF chip under human supervision.

Lu: What’s really important is that they tackle the full lifecycle, from ingesting existing engineering documentation through topology selection and ultimately generating a testbench and optimizing sizing based on verified data.

Meng: They show that this isn't just one AI guessing; it’s a structured orchestration where different agents hand off tasks to each other, which makes the process much more traceable.

Lalam: I think the implication is that we can start seeing much faster turnaround times for complex circuit designs because the AI is doing all the iterative exploration and validation work.

Tom: The authors focus on demonstrating automated topology generation and specification-driven design space exploration using this flow on GF22FDSOI sixty GHz wideband LNAs.

Jane: They show substantial reductions in design effort while still achieving signoff-quality verification, completing the entire campaign in about two hours of wall-clock time at an estimated cost of.twenty.

Lu: It really shows how combining retrieval augmented generation with structured agents can provide an evidence-based foundation for design decisions, cutting down on unsupported assumptions.

Meng: For engineers looking at this, it means less time spent chasing the perfect initial layout and more time spent directing the AI toward specific performance goals.

Tom: The authors are building a flow that encompasses knowledge ingestion, schematic generation, simulation-driven optimization, and trusted knowledge accumulation all in one agentic system.

Jane: It’s about showing how structured AI orchestration can take the labor-intensive parts of analog circuit design and make them significantly more efficient.

Lu: The authors are setting up a framework that combines multimodal retrieval with sequential, specialized agents to tackle complex design challenges autonomously.

Meng: This feels like it could drastically reduce the time spent on initial concept generation and layout exploration for new RF architectures.

Lalam: And I see this advancing the culture of design by making complex optimization accessible through these structured, agentic workflows.

Awani Khodkumbhe, Yunfei Feng, Raj Rangarajan, Kevin Wang, Kamal Sahota

Qualcomm Technologies, Inc. · UC Berkeley

cs.AR, cs.AI, cs.LG, cs.MA, cs.SY, eess.SY

Submitted: 2026-10-07

Updated: 2026-10-07

The gist: The gist: This work introduces RFChipAgent, a first-of-its-kind multi-agentic AI flow for end-to-end design automation of Analog/RF circuits, which autonomously orchestrates the complete design flow

Key concepts

Knowledge Ingestion Agent (Multimodal RAG)
This agent uses a multimodal Retrieval-Augmented Generation (RAG) system with private indexing to extract design knowledge from engineering documents. It ensures that retrieved information is traceable back to its original source, preventing errors and hallucinations when making design decisions.
Topology Agent
This agent takes target circuit specifications and uses retrieved design knowledge and rules to select the best schematic structure. It performs sequential checks, estimating stage counts based on power budgets and prioritizing devices that offer the best noise performance.
Trust-Scored Database
This database stores verified simulation data, accumulating performance metrics across trials. A trial is only accepted into the 'good set' if it passes a trust-score threshold calculated from execution and proof scores, ensuring only reliable data informs the final design.
Sizing Optimizer (TPE/CMA-ES)
This engine uses a two-stage optimization approach: Tree-structured Parzen Estimator (TPE) for broad exploration and Covariance Matrix Adaptation Evolution Strategy (CMA-ES) for fine local tuning. It optimizes cell sizing by minimizing a combined quality metric based on five performance indicators.

Terminology

Summary

The gist: This work introduces RFChipAgent, a first-of-its-kind multi-agentic AI flow for end-to-end design automation of Analog/RF circuits, which autonomously orchestrates the complete design flow under human supervision.

How it works

RFChipAgent is built around four technical pillars that replace the traditional trial-and-error design methodology with a systematic, self-improving agentic workflow. These pillars include a multimodal retrieval-augmented generation (RAG) subsystem for knowledge extraction, a topology agent for selection, and an automated schematic and testbench agent. Furthermore, it incorporates a closed-loop hybrid sizing engine and a trust-scored simulation database to accumulate verified performance data.

Knowledge Ingestion

The Knowledge Ingestion Agent utilizes a multimodal RAG subsystem with private per-document FAISS indexing to extract design knowledge from existing engineering documentation. This approach addresses the risk of hallucination by ensuring that every retrieved chunk retains its source-document identity throughout retrieval and reasoning, which significantly reduces the risk of cross-document attribution errors. For instance, in the LNA case study, retrieved design knowledge directly influenced the topology agent’s architectural decisions by providing evidence that transformer-based matching is a widely adopted solution for wideband 60 GHz operation and demonstrating the suitability of the technology node.

Topology Selection and Design Strategy

The Topology Agent converts target LNA specifications into a schematic design strategy using retrieved design knowledge and structured RF design rules. This agent employs sequential checks, including stage count estimation based on power budget, active device selection prioritizing noise performance, and passive network assignment for input/interstage/output matching. For example, the agent uses PDK priors and power consumption budget to estimate whether a 2-stage design can meet the gain targets before adding a third stage when dealing with the LNA example.

Schematic Generation and Optimization

The Schematic and Testbench Generation Agent separates cell validation, schematic generation, and testbench assembly into independently auditable stages. Before schematic generation, a validation skill maintains inventories of active cells and passive matching-network cells, ensuring that All active cells expose a standardized 10-pin interface and all passive cells expose a standardized 7-pin interface for interchangeable instantiation. The Sizing Optimizer employs a two-stage optimization approach: Tree-structured Parzen Estimator (TPE) for global exploration and Covariance Matrix Adaptation Evolution Strategy (CMA-ES) for local exploitation, operating within a simulator-in-the-loop framework. The objective function combines five quality metrics using a harmonic mean, defined by the formulation Qtotal = 5/ (1 + QNF + 1/QS21 + 1/S11 + 1/Qflat + 1/PDC).

Trust-Scored Database and Validation

A trust-scored simulation database accumulates verified performance data across trials and builds an adaptive optimization model. Every trial is only admitted to the good set G or bad set B if it clears a trust-score threshold, calculated as T(d) = 0.7Texec(d) + 0.3Tprov(d). Per-trial physical validity gates are executed after each simulation trial and before objective-function evaluation, including a DC operating-point check and a stability check that rejects trials if "mumin < 1 or if the global S11 exceeds 0 dB at any frequency within this range".

The experiment validated RFChipAgent on GF22FDSOI 60 GHz wideband Low Noise Amplifier (LNA) topologies, demonstrating automated topology generation, specification-driven design-space exploration, and simulator-guided optimization. Experimental results show substantial reductions in design effort while maintaining signoff-quality verification. The campaign completed in approximately 2 hours of wall-clock time at an estimated cost of 156.20 dollars, which is a substantial improvement over manual labor-intensive circuit design.

References

[1] J. Gao, W. Fu, X. Guo, W. Cao, and X. Zhang Building Reasoning LLMs for Hardware Design Generation via Function-Aligned Differentiated Revision IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2025

[2] S. Wang, Q. Li, H. He, J. Gao, Z. Wang, Y. Sun, X. Zhang Building Multi-Agent Generative Synthesis for Analog/RF Circuit from Scalable Topology Generation to Efficient Inverse Design IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2025

[3] J. Gao, W. Cao, and X. Zhang RoSE Robust Analog Circuit Parameter Optimization with Sampling-Efficient Reinforcement Learning ACM/IEEE Design Automation Conference (DAC) 2023

[4] W. Fu, S. Li, K. Yang, X. Zhang, Y. Jin, and X. Guo Building Reasoning LLMs for Hardware Design Generation via Function-Aligned Differentiated Revision IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2025

[5] V. Chenna and H. Hashemi A Nonintuitively Frequency-Staggered Wideband mm-Wave Low-Noise Amplifier IEEE International Solid-State Circuits Conference (ISSCC) 2026

[6] P. Abbineni, S. Aldowaish, C. Liechty, S. Noorzad, A Ghazizadeh Ghalati, and M Fayazi MuaLLM A Multimodal Large Language Model Agent for Circuit Design Assistance with Hybrid Contextual Retrieval-Augmented Generation Asia South Pacific Design Automation Conference (ASP-DAC) 2026

[7] J. Gao, W. Fu, X. Guo, W.

Improvements for AI systems

  1. textbfKnowledge Ingestion Augmentation with Provenance Tracking: The RAG Enhancement Engine (RAGE). It improves reliability by ensuring topology descriptions, performance metrics, and design insights remain explicitly traceable to their original references by decoupling retrieval from inference through a hybrid RAG agent and ReAct workflow, specifically addressing the risk of cross-document attribution errors that can arise in conventional merged-index RAG systems.

  2. textbfTopology Agent Refinement via Physics-Aware Constraint Prioritization. The system can better select topologies by prioritizing design decisions based on physics-aware checks, such as using PDK priors and power consumption budget to estimate whether a 2-stage design can meet the gain targets before adding a third stage, ensuring that the agent's selection process is guided by causally ordered design decisions.

  3. textbfSchematic Generation Robustness through Automated Cell Validation Pipelines. The system can generate more reliable schematics by implementing stringent pre-generation checks, where All active cells expose a standardized 10-pin interface and all passive cells expose a standardized 7-pin interface, ensuring that Cells that fail any verification step are flagged and automatically rebuilt until a verified implementation is available.

  4. textbf Sizing Optimization via Adaptive Exploration Strategy. The sizing optimizer can efficiently navigate the high-dimensional design space by employing a two-stage optimization approach: using Tree-structured Parzen Estimator (TPE) optimization is first used for global exploration followed by Covariance Matrix Adaptation Evolution Strategy (CMAES) applied for local exploitation and fine-grained refinement.

  5. textbf Closed-Loop Optimization Integrity via Trust Score Gating. The system can prevent the propagation of invalid designs by ensuring that optimization only proceeds with verified data, as trials are admitted to the good set G or bad set B if it clears the trust-score threshold, where execution integrity and data provenance are weighted to ensure only results from trials that cleared both the physical-validity gates and the trust threshold are used.

Related papers