Bit-Accurate Modeling of GPU Matrix Multiply-Accumulate Units: Demystifying Numerical Discrepancy and Accuracy

arXiv:2511.10909 · cs.AR, cs.LG, cs.NA, math.NA · Submitted 2025-11-14 · Read on arXiv

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Introduction to the show: ident: AI Radio. Generated commentary on the latest Artificial Intelligence papers.

Tom: Today's paper: "Bit-Accurate Modeling of GPU Matrix Multiply-Accumulate Units".

Jane: Bit-accurate models of GPU matrix multiply-accumulate units (MMAUs) are proposed using a closed-loop feature probing framework to diagnose and understand numerical discrepancies and accuracy issues across different hardware platforms.

Tom: First, who's behind it and why it matters.

Paper summary: Tom: So, we’ve covered the high points, but let’s really nail down what this paper is all about by looking at the core claims of "Bit-Accurate Modeling of GPU Matrix Multiply-Accumulate Units: Demystifying Numerical Discrepancy and Accuracy." Essentially, the thesis is that modern AI accelerators use MMAUs whose internal floating-point arithmetic behaviors are largely undocumented, which leads to numerical discrepancies across hardware generations.

Jane: Right, Tom; they argue that this lack of documentation causes issues like poor summation precision in FP8 operations or subnormal flushing in FP16 operations, and this paper claims it provides the first bit-accurate arithmetic models for instruction-level MMA operations on ten different GPU architectures spanning NVIDIA Volta to RTX Blackwell and AMD CDNA1 to CDNA3.

Lu: The core contribution here is proposing the closed-loop feature probing framework, CLFP, which is a generic methodology designed to construct complete arithmetic behavior models of MMA operations by integrating arithmetic feature probing with iterative model refinement.

Meng: I see that as a systematic approach rather than just an ad-hoc investigation; it suggests they have a repeatable process for deriving these complex behaviors.

Lalam: That systematic nature is what makes the research powerful because it moves beyond observation and toward creating predictive, verifiable models for the underlying hardware operations.

Tom: Exactly! They walk through four testing-based steps: confirming computational independence, determining summation order and arity, probing detailed arithmetic features like Summation Precision and Rounding Mode using edge cases.

Jane: And that probing leads to derived bit-accurate models categorized into three types: those based on binary Add and Mul operations, ternary FMA operations, and N-ary FDPA operations such as Exact FDPA or Group-Scaled Truncated FDPA.

Lu: The paper claims these models explain previously observed numerical discrepancies across accelerators by detailing how the MMAUs produce specific output values for the same input, like the six different values mentioned in page one of that work reads: "of their arithmetic behaviors (§four)".

Meng: Knowing those specific output outcomes is critical because it allows us to map exactly which hardware implementation corresponds to which mathematical result.

Lalam: This level of detail helps build a shared understanding across the industry about how these accelerators behave when handling standard AI workloads.

Tom: And what they uncover through these models is that only FP64/FP32 MMA instructions maintain consistent behavior because they adhere to standard FMA operations, whereas mixed-precision instructions show discrepancies due to different elementary operations and parameters.

Jane: The paper also quantitatively analyzes the sources of numerical errors, revealing four types of precision bottlenecks and one type of asymmetry that significantly degrade accuracy in page one of that work reads: "The white-box models also enable us to quantitatively analyze the sources of numerical errors, revealing four types of precision bottlenecks and one type of asymmetry that significantly degrade the numerical accuracy of MMAUs (§six)".

Lu: They provide software workarounds, mitigation methods, and design guidance directly stemming from this analysis for future MMAUs.

Meng: So, we aren't just observing problems; they are actively designing solutions based on a deep understanding of the root causes.

Lalam: This entire body of work contributes to making the AI infrastructure more numerically sound and trustworthy for demanding applications.

Conclusion: Tom: So, wrapping up our discussion on "Bit-Accurate Modeling of GPU Matrix Multiply-Accumulate Units: Demystifying Numerical Discrepancy and Accuracy," the authors, Xie et al., have delivered a comprehensive analysis of internal hardware behavior that was previously hidden.

Jane: It’s about demystifying the numerical discrepancies by building these bit-accurate models, which essentially gives us a white-box view of what's happening inside the MMAUs, moving past just observing errors to actually understanding their source.

Lu: The paper demonstrates that for mixed-precision instructions, accuracy issues stem from different elementary operations and parameters within the units, which is a key insight into hardware design choices.

Meng: For us in engineering, this means we can start using these models to predict where numerical instability might arise before we even start extensive testing on new chip designs.

Lalam: This research has major implications for the future culture of AI by providing a verifiable foundation for numerical stability, helping us build more robust and trustworthy AI systems that perform better everywhere.

Tom: Ultimately, this work provides software workarounds, mitigation methods, and design guidance aimed at improving the next generation of MMAUs based on this deep understanding of their arithmetic structure.

Jane: And by giving us these models for ten architectures, it allows researchers to systematically analyze and predict accuracy issues across a wider range of hardware platforms.

Lu: It suggests that the field still needs a systematic approach for deriving white-box executable models because feature probing alone has limitations in constructing reliable end-to-end models, as noted in page two of that work reads: "First, they focus on partial arithmetic features for a limited set of architectures, which are incomplete for constructing white-box executable models."

Meng: That limitation is important; it tells us that feature probing isn't the final answer on its own when you need a complete picture, which reinforces the need for this kind of closed-loop refinement.

Lalam: So this paper sets a new standard for how we approach hardware understanding in AI development by emphasizing systematic model construction over just hoping empirical testing will eventually reveal all the issues.

cs.AR, cs.LG, cs.NA, math.NA

Submitted: 2025-11-14

Updated: 2026-09-28

Comments: camera-ready for MICRO 2026

Code: https://github.com/microsoft/MMA-Sim

License: http://creativecommons.org/licenses/by-nc-sa/4.0/

Importance score: 91/100

The gist: Bit-accurate models of GPU matrix multiply-accumulate units (MMAUs) are proposed using a closed-loop feature probing framework to diagnose and understand numerical discrepancies and accuracy issues

Key concepts

Closed-Loop Feature Probing (CLFP): A generic methodology that builds an arithmetic behavior model by iteratively testing edge cases. It decomposes complex MMA operations into simpler components, probes features like rounding modes and summation order, and then revises the model until it accurately predicts the operation's behavior.
MMAU Models ($\Phi$): These are bit-accurate mathematical models for GPU matrix multiply-accumulate units. The framework creates three types of models based on elementary operations (like binary add/mul or ternary FMA) to precisely describe how the hardware performs arithmetic, including specific rounding and flushing behaviors.
Numerical Discrepancy Analysis: This process identifies why different GPU architectures produce different numerical results. The models expose error sources, such as subnormal flushing in FP8 operations or rounding errors in FMA instructions, providing a white-box understanding of accuracy issues.
Feature Probing: The act of testing the MMAU with specific inputs and edge cases to infer underlying arithmetic features. This includes testing different summation orders, determining tie-breaking rules, and observing how the hardware handles operations like adding a very small number (epsilon) to understand its precision limits.

Terminology

Accuracy — 40× in this paper · explained in 1 episode
Core — 37× in this paper · explained in 2 episodes
Closed-Loop Feature Probing — 10× in this paper
Verification — 3× in this paper · explained in 2 episodes
IEEE International Parallel and Distributed Processing Symposium — 1× in this paper
In International Symposium on Computer Architecture — 1× in this paper
Large Language Models (LLMs) — 1× in this paper · explained in 6 episodes
Reinforcement Learning — 1× in this paper · explained in 4 episodes

Summary

Bit-accurate models of GPU matrix multiply-accumulate units (MMAUs) are proposed using a closed-loop feature probing framework to diagnose and understand numerical discrepancies and accuracy issues across different hardware platforms. This work is critical because it provides the first bit-accurate arithmetic models for instruction-level MMA operations on ten GPU architectures, enabling white-box numerical error analysis, revealing precision bottlenecks, and guiding future hardware design.

The gist

This paper proposes closed-loop feature probing (CLFP), a generic framework for constructing complete arithmetic behavior models of MMA operations by integrating arithmetic feature probing with iterative model refinement to derive bit-accurate models for instruction-level MMAUs on NVIDIA and AMD GPUs.

The Problem and Motivation

Modern AI accelerators rely on MMAUs, but their internal floating-point arithmetic behaviors are poorly documented, leading to numerical discrepancies across vendors and architectural generations that can cause training instability. These discrepancies manifest as issues like poor summation precision in FP8 MMA operations or subnormal flushing in FP16 operations. The lack of a white-box understanding makes numerical analysis empirical and reactive, necessitating a systematic white-box model to predict accuracy and design principled mitigations.

The Closed-Loop Feature Probing (CLFP) Framework

The CLFP framework is a generic methodology designed to build the arithmetic behavior model Φ such that Φ(A, B, C) = MMA-Interface(A, B, C). The workflow consists of four testing-based steps:

Confirming Computational Independence: This step decomposes the MMA operation into independent dot-product-accumulate operations.
Determining Summation Order and Arity: This step transforms the dot-product-accumulate operation into a summation tree by constructing specific inputs to infer the order of summation, including distinguishing between swamped and non-swamped n-term fused summations.
Probing Arithmetic Features: This step probes detailed arithmetic behavior using edge cases to infer features such as Summation Precision (e.g., testing Add(U, ε) for binary additions), Rounding Mode (testing four sets of inputs for RU, RD, RZ, RA, RN), and Tie-breaking Rule.
Validation and Revision: The model is validated through randomized testing (one million tests plus continuous testing). If verification fails, the model is revised by debugging the failing test case to infer new arithmetic features and repeating the loop until validation passes.

Derived Bit-Accurate Models

The CLFP framework constructs bit-accurate models for every instruction, categorized into three types based on elementary operations:

Models Based on Binary Add and Mul Operations (e.g., ΦFTZ-AddMul), which describe flush-to-zero addition and multiplication behaviors, revealing that input subnormals are flushed to positive zeros before multiplication.
Models Based on Ternary FMA Operations (e.g., ΦFMA), which model standard FMA operations as a chain of FMAs with round-to-nearest-ties-to-even (RNE) mode.
Models Based on N-ary FDPA Operations (e.g., ΦTR-FDPA, ΦGST-FDPA), which describe fused dot-product operations using various variants like Exact FDPA (E-FDPA), Truncated FDPA (T-FDPA), Scaled Truncated FDPA (ST-FDPA), and Group-Scaled Truncated FDPA (GST-FDPA).

Numerical Discrepancy Analysis and Error Sources

The white-box models expose hardware perspectives on numerical discrepancies, showing that only FP64/FP32 MMA instructions maintain consistent behavior due to adopting standard FMA operations. For mixed-precision instructions, discrepancies arise from different elementary operations and parameters. Key error sources include:

(In ΦFTZ-AddMul):

FlushSubnormal (input subnormal flushing function), with an error bound of MinNormal(F).
Add/Mul operations, with an error bound of 0.5 ulpFP32 = 0.5 × 2 e result - 2 33.

(In ΦFMA and ΦE-FDPA):

Output rounding, with an error bound of 0.5 ulpFP64 or 0.5 ulpFP32 (for RNE).

(In ΦT-FDPA and other variants of ΦFDPA):

Fused summation, with an error bound of at most (L + 1)2 e max - F fractional bits.
Output rounding, with bounds depending on the mode (0.5 ulp for RNE or 1 ulp for RZ).

Improvements for AI systems

As a fastidious and diligent researcher, I have analyzed this groundbreaking work on bit-accurate modeling of GPU Matrix Multiply-Accumulate Units (MMAUs). The core contribution is the Closed-Loop Feature Probing (CLFP) framework, which derives white-box models for hardware arithmetic behaviors from black-box testing.

Here are the specific improvements and what they enable in AI systems:

Enhance Reproducibility and Cross-Platform Portability:

A major bottleneck is cross-vendor/cross-generation numerical discrepancy. The derived bit-accurate models allow developers to predict, isolate, and mitigate these discrepancies at the hardware level rather than empirically debugging them in software.

Improve Training Stability in Mixed Precision:

The paper identifies specific precision bottlenecks (e.g., subnormal flushing in FP16 MMA on AMD CDNA2 or poor summation precision in FP8 MMA on NVIDIA Hopper). By understanding the exact arithmetic behavior (summation order, rounding modes), developers can implement targeted mitigations like using higher-precision accumulation or switching to more stable instruction variants.

Enable Proactive Hardware Design Guidance:

For future AI accelerator designers, the paper provides concrete design guidance. Designers can avoid specific risky arithmetic configurations (like those in Table 10) and adopt internal encoding schemes (like sign-and-magnitude instead of two's complement for symmetric rounding) to ensure consistent numerical accuracy across different hardware generations.

Develop Precision-Aware Software Workarounds:

Instead of broad, inefficient workarounds, the CLFP framework provides instruction-specific models (e.g., identifying when a specific FMA variant is causing truncation). This allows software developers to switch between precise or stable MMA instructions dynamically based on the target architecture and data type being used in a specific layer of a DNN.

Facilitate Rigorous Numerical Error Analysis:

The white-box models allow for quantitative analysis of error sources (e.g., quantifying the error bound from fused summation vs. output rounding). This moves numerical debugging from guesswork to precise mathematical quantification, enabling developers to prioritize fixes based on the most significant sources of numerical drift.

The resulting improved AI systems can:

Run deep learning models (especially LLMs) with significantly higher and more consistent training accuracy across different GPU vendors and architectures (NVIDIA vs. AMD).
Achieve better model reproducibility, reducing the need for extensive, time-consuming retraining cycles to resolve numerical inconsistencies between platforms.
Support the deployment of low-precision formats (FP8/FP4) with confidence in their numerical stability by knowing exactly which operations are prone to catastrophic cancellation or flushing subnormals on a given hardware unit.
Allow for more robust and accurate mixed-precision training regimes, potentially reducing the reliance on costly FP32 accumulation buffers by using architecture-aware, precision-optimized MMA instructions.

Abstract

Modern AI accelerators rely on matrix multiply-accumulate units (MMAUs), such as NVIDIA Tensor Cores and AMD Matrix Cores, to accelerate deep neural network workloads. MMAUs expose only instruction-level or API-level interfaces of matrix multiply-accumulate (MMA) operations, while leaving internal floating-point arithmetic behavior undocumented. Consequently, MMAUs across vendors and architectural generations often produce numerical discrepancies for identical inputs, and sometimes exhibit reduced numerical accuracy that can cause training instability. Diagnosing and understanding the root causes of these effects is challenging without white-box models of their arithmetic behavior. This paper proposes closed-loop feature probing (CLFP), a generic and systematic framework for constructing bit-accurate arithmetic behavior models of MMA operations. Based on this framework, we analyze all MMA instructions on ten GPU architectures spanning NVIDIA Volta through RTX Blackwell and AMD CDNA1 through CDNA3, and derive the first bit-accurate arithmetic models for these MMAUs. Our models explain previously observed cross-platform numerical discrepancies and accuracy issues, enable white-box numerical error analysis, reveal four types of precision bottlenecks and one type of numerical asymmetry, and inform software workarounds as well as design suggestions for future MMAUs. This work is open-source at https://github.com/microsoft/MMA-Sim