Validation and Simulation Catch Different Errors: Four Levels of Evaluation for LLM-Generated Circuits
cs.AR, cs.AI
Submitted: 2026-09-21
Updated: 2026-09-21
Code: https://github.com/wokwi/avr8js
Terminology
Sources
- AnalogCoder: Analog Circuit Design via Training-Free Code Generation
- LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits
- LaMAGIC2: Advanced Circuit Formulations for Language Model-Based Analog Topology Generation
- AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies
- CktGen: Automated Analog Circuit Design with Generative Artificial Intelligence
- AnalogAgent: Self-Improving Analog Circuit Design Automation with LLM Agents
- AnalogMaster: Large Language Model-based Automated Analog IC Design Framework from Image to Layout
- Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
- AMSnet 2.0: A Large AMS Database with AI Segmentation for Net Detection
- Chip-Chat: Challenges and Opportunities in Conversational Hardware Design
- ChipNeMo: Domain-Adapted LLMs for Chip Design
- VerilogEval: Evaluating Large Language Models for Verilog Code Generation
- RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
- Teaching Large Language Models to Self-Debug
- Reflexion: Language Agents with Verbal Reinforcement Learning
- Self-Refine: Iterative Refinement with Self-Feedback
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