LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration
cs.AR, cs.AI, cs.SE
Submitted: 2026-08-27
Updated: 2026-08-27
Comments: 16 pages, 4 figures, 2 tables (in Supplementary Information); interactive version of Fig. 2 at https://mattycode101.github.io/LLMs_in_Digital_EDA_Perspective/
Project page: https://mattycode101.github.io/LLMs_in_Digital_EDA_Perspective
License: http://creativecommons.org/licenses/by/4.0/
The gist: Electronic design automation (EDA) has advanced engineering productivity through successive generations of tooling that progressively automate synthesis, optimisation, and verification.
Terminology
Abstract
Electronic design automation (EDA) has advanced engineering productivity through successive generations of tooling that progressively automate synthesis, optimisation, and verification. Large language models (LLMs) extend this trajectory by enabling direct translation from design intent to hardware implementations. In most of the EDA literature, LLM-based solutions are typically assisting siloed design stages or tasks, however this obscured the drivers by which capability emerges and systems scale. In this Perspective, we instead define three hierarchical roles that reveal how capability accumulates: a Generator that produces design artifacts in a single pass, an Agent that refines outputs through iterative tool feedback, and an Orchestrator that coordinates decisions across EDA-stages. Across published systems, this reveals a syntax trap in which models are trained to produce plausible code rather than physically correct hardware, compounded by fragmented tools and loss of design context that obscure how decisions affect later stages. Comparisons across the three roles show that current approaches struggle to scale to industrial designs, motivating a shift towards a standardised, physics-aware orchestrator that connects tools and agents across the EDA flow for more reliable and accessible hardware design.
Sources
- Machine Learning for Electronic Design Automation: A Survey
- The Dawn of Agentic EDA: A Survey of Autonomous Digital Chip Design
- The Impact of AI on Developer Productivity: Evidence from GitHub Copilot
- Towards Optimal Circuit Generation: Multi-Agent Collaboration Meets Collective Intelligence
- ChipNeMo: Domain-Adapted LLMs for Chip Design
- RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models
- Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction
- Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback
- ChipGPT: How far are we from natural language hardware design
- Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
- ResBench: Benchmarking LLM-Generated FPGA Designs with Resource Awareness
- AutoEDA: Enabling EDA Flow Automation through Microservice-Based LLM Agents
- RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Experts
- RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs
- VerilogEval: Evaluating Large Language Models for Verilog Code Generation
- VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts
- AutoChip: Automating HDL Generation Using LLM Feedback
- MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization
- ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning
- VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
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