Nearest-neighbour gates are all you need: High-rate quantum low-density parity-check codes on a planar grid

arXiv:2606.19482 · quant-ph · Submitted 2026-06-17 · Read on arXiv

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Introduction to the show: ident: Quantum Radio. Generated commentary on the latest quantum physics and condensed matter papers.

Kai: Today's paper: "Nearest-neighbour gates are all you need".

Mira: High-performance quantum low-density parity-check codes promise substantial reductions in the overhead of fault-tolerant quantum computation, but most constructions require long-range connectivity or qubit shuttling,

Kai: First, who's behind it and why it matters.

Paper summary: Mira: Thinking about the title, "Nearest-neighbour gates are all you need: High-rate quantum low-density parity-check codes on a planar grid," it really captures the essence of the paper's contribution, which is simplifying the hardware requirements for these kinds of codes.

Kai: Right, and when we look at what this means in simpler terms, it’s that we’ve found a way to implement powerful quantum error correction schemes using only local gates on a grid structure without demanding complex long-range physical connections or moving qubits around constantly.

Lev: I see the implication for running these codes: if the syndrome extraction dynamics are inherently local and governed by nearest-neighbour walks, then we bypass the need for complicated global control lines that usually bottleneck scaling up error correction systems on current hardware.

Mira: The authors’ work essentially shows how to design a low-density parity-check code structure where the physical implementation constraints—the planar grid and nearest-neighbour gates—naturally align with the required syndrome measurement process, which is a very neat conceptual alignment.

Kai: So, for me, the main point is that they've provided a constructive method: directional words define both the stabilizer structure and how you measure it simultaneously using local operations on a square grid, which cuts down on complexity substantially.

Lev: That constructive aspect is what makes it relevant for error correction researchers because it gives us a tangible framework to start designing actual circuits instead of just theoretical bounds; we can see how the complexity scales based on the distance d.

Mira: And from a theoretical perspective, the finding that these directional tile codes outperform rotated surface-code patches in code efficiency suggests that there's structural beauty in how these specific lattice constructions interact with local connectivity.

Kai: I think the real impact is showing that we don't have to sacrifice locality for performance when designing fault-tolerant quantum computation; this moves us closer to realizing practical, scalable hardware on existing platforms.

Conclusion: Kai: So, to wrap up this discussion on "Nearest-neighbour gates are all you need," we've seen how these codes work without needing those long-range connections we usually fear in superconducting circuits.

Mira: I think the paper really nails it by showing that their construction of check-data connectivity is dynamic, using nearest-neighbour iSWAP walks to handle both the stabilizer supports and the measurements on a square grid.

Lev: From an error correction standpoint, this is significant because it means we don't have to worry about complex routing overhead that often kills our scaling efforts on real hardware.

Kai: Exactly, and when you look at the results, they show these directional tile codes can actually beat rotated surface-code patches in terms of code efficiency when you push them to realistic error rates.

Mira: That efficiency gain is what's really interesting; it suggests that the structural arrangement of these specific planar layouts offers a better trade-off between code size and resource usage than we previously thought.

Lev: I mean, if we can achieve those error rate reductions by just using local gates, then the path to building fault-tolerant systems on current architectures looks much more viable.

Kai: It really points toward a design philosophy where the hardware constraints aren't an obstacle but are actually being leveraged to create a more efficient code structure.

Mira: The authors' focus on directional words defining both the stabilizer structure and the measurement walk is a very elegant way to simplify that complex mapping between theory and physical implementation.

Lev: It gives us a concrete mechanism for how to handle syndrome extraction that doesn't require any kind of qubit shuttling, which is a massive win for experimentalists.

Kai: So, this paper suggests we can design codes that are naturally compatible with the nearest-neighbour constraints of our current hardware while still achieving high performance.

Mira: And it leaves us wondering how far this idea extends beyond the square grid structure they used in their construction to other types of physical layouts.

1Dahlem Center for Complex Quantum Systems at Freie Universitat Berlin · Quantum Software Lab at The University of Edinburgh · IQM Quantum Computers at IQM Quantum Computers in Munich · Institute of Mathematics at Johannes Gutenberg-Universitat Mainz, Helmholtz-Zentrum Berlin fur Materialien und Energie

quant-ph

Submitted: 2026-06-17

Updated: 2026-10-02

Comments: 9+5 pages, 9 figures, 7 tables

License: http://creativecommons.org/licenses/by/4.0/

Importance score: 85/100

The gist: High-performance quantum low-density parity-check codes promise substantial reductions in the overhead of fault-tolerant quantum computation, but most constructions require long-range connectivity or

Key concepts

Directional Words: These are ordered strings of lattice steps that geometrically trace a connected path on a square grid. Algebraically, this string defines the support structure of a stabilizer. Pairing these words on primal and dual lattices creates the full CSS stabilizer structure.
Nearest-Neighbour iSWAP Walks: Instead of requiring long-range connections, these walks use only local nearest-neighbor gates (iSWAPs) to define both where the stabilizers are located and how they are measured. This dynamic approach eliminates the need for a complex, long-range hardware graph.
Code Efficiency Ratio: This metric compares the performance of a new code construction against existing ones, like surface codes. The paper shows that certain tile codes achieve an efficiency ratio nearly ten times larger than rotated surface-code patches at the same code level.
Routing Overhead Scaling: The number of qubits needed for routing (moving check data) scales relatively slowly with the code size, specifically $O(\sqrt{n})$ or $O(d)$. This demonstrates that even with local constraints, the overhead remains manageable and can be optimized using techniques like 'route window shortening'.

Terminology

Trace — 6× in this paper · explained in 2 episodes
Benchmark — 5× in this paper · explained in 2 episodes
Pruning — 5× in this paper · explained in 4 episodes
Core — 2× in this paper · explained in 2 episodes
Alignment — 1× in this paper · explained in 1 episode

Summary

The key idea is to generate check-data connectivity dynamically: nearest-neighbour iSWAP walks both define the stabiliser supports and implement their measurement, avoiding the need for a long-range hardware graph.

How it works

The core innovation introduces a family of quantum low-density parity-check codes that combine planar open-boundary layouts, finite-size advantages over surface codes, and syndrome extraction using only nearest-neighbour gates on a square grid of qubits. The key mechanism is to generate check-data connectivity dynamically: nearest-neighbour iSWAP walks both define the stabiliser supports and implement their measurement, avoiding the need for a long-range hardware graph. This approach achieves optimal constant-depth stabiliser measurement, independent of code size, and naturally removes leakage by exchanging the role of check and data qubits at each syndrome extraction round.

Code Construction via Directional Words

The construction is organized around directional words, which are defined as an ordered string of lattice steps. Geometrically, this string traces a bounded-size connected string on the square lattice; algebraically, it defines the support of a stabiliser. The paired X- and Z-type checks are obtained by placing the same word on primal and dual lattices. This ensures that one directional word defines both the Calderbank–Shor–Steane (CSS) stabiliser structure and the spacetime walk used to measure it.

Syndrome Extraction Circuit Implementation

The syndrome extraction circuit is explicitly implemented using nearest-neighbour iSWAP gates, which are locally equivalent to a CXSWAP gate. The algorithm iterates through the directional word, applying one nearest-neighbour directional layer for each step. The sequence of operations is governed by Algorithm 1, which dictates how check qubits move along the prescribed direction by nearest-neighbour exchange operations, interacting with data qubits via CX gates whenever the walk encounters a data qubit.

Performance Benchmarks and Advantages

The paper demonstrates that directional tile codes perform strongly under both code-level and implementation-level benchmarks. At the code level, they identify compact instances such as the [[323, 14, 15]] code, whose code-efficiency ratio is nearly an order of magnitude larger than that of a rotated surface-code patch. At the implemented-circuit level, circuit-level simulations show that these layouts can fall below rotated surface-code footprint curves at a realistic physical error rate p = 0.001. Specifically, at a footprint of around 30 circuit qubits per logical qubit, the best directional tile-code layouts reduce the per-logical per-round logical error rate by up to three orders of magnitude relative to rotated surface-code memories encoding the same number of logical qubits.

Routing Overhead and Optimization

The routing overhead introduced by this scheme is boundary dominated and scales linearly with the relevant code distances. The paper proves a general scaling bound: the number n r of routing qubits required for nearest-neighbour syndrome extraction satisfies n r = O (√n). This scaling is further refined, showing that for balanced families, the overhead reduces to n r = O (d), where d is the relevant distance scale. The authors employ two optimization procedures: route window shortening and trace pruning, which are combined iteratively to reduce routing overhead, demonstrating that the advantages of qLDPC codes can be retained under the same square-grid nearest-neighbour constraint that makes the surface code hardware-compatible.

Logical Operations and Automorphisms

The construction allows for logical operations through structural descriptions derived from tile codes. A first route involves a derived automorphism [50], where the tile-code patch is temporarily enlarged along one boundary, inducing a non-trivial Clifford action on encoded qubits. Furthermore, palindromic directional words induce a reflection of the physical qubit layout that preserves the stabiliser group, defining a code automorphism. This symmetry allows for logical operations to be realized through permutations or re-indexing of physical qubits rather than requiring actual SWAP circuits in the original planar layout.

Future Directions

The research suggests that qLDPC-like finitesize advantages can survive the stringent locality constraints of planar superconducting hardware when the code, native gates, and syndrome-extraction dynamics are co-designed. Future work is suggested to include a more systematic search over words, layouts, schedules, and routing optimisations and to investigate code-switching techniques between directional tile codes defined by different words. Additionally, optimizing these circuits under biased noise or hardware-calibrated error models remains a natural direction.

Improvements for AI systems

Here are the specific improvements to AI systems that could be derived from this scientific paper, along with what those improved systems could achieve:

The core improvement is in developing a new class of fault-tolerant quantum memory architectures that overcome the connectivity limitations of superconducting hardware by dynamically generating required interactions locally using nearest-neighbor gates (iSWAP).
This enables the creation of high-performance Quantum Low-Density Parity-Check (qLDPC) codes that are natively compatible with strictly planar, nearest-neighbor physical layouts, unlike surface codes which often require long-range connectivity or complex qubit shuttling.
The improved system can function as a fault-tolerant quantum computer capable of storing and manipulating many logical qubits with significantly reduced physical overhead compared to current state-of-the-art surface code patches.
Specifically, the system can achieve a per-logical per-round logical error rate reduction of up to three orders of magnitude (relative to rotated surface codes) when operating at a footprint of approximately 30 circuit qubits per logical qubit under realistic physical error rates (e.g., 0.001).
The system can be designed with integrated leakage mitigation strategies by dynamically exchanging the roles of data and check qubits during syndrome extraction, which naturally removes population from higher excited states in superconducting systems.
The system can be optimized for specific noise profiles (biased noise, coherent circuit noise) by leveraging the structural properties of directional tile codes and their associated automorphism groups to guide optimal syndrome-extraction schedules and routing qubit placement (trace pruning).
The improved system can perform complex logical operations efficiently by utilizing derived automorphisms from the underlying tile code structure, allowing for controlled deformations that decompose into low-overhead logical CNOT gates.

In summary, the improved AI system is a quantum memory and computation engine that utilizes directional tile codes to store and process large numbers of logical qubits on planar hardware with high efficiency and resilience against noise, effectively bridging the gap between high-rate qLDPC codes and the strict locality constraints of current superconducting quantum processors.

Abstract

High-performance quantum low-density parity-check codes promise substantial reductions in the overhead of fault-tolerant quantum computation, but most constructions require long-range connectivity or qubit shuttling, both of which are difficult to realise in superconducting architectures. Here we introduce a family of quantum low-density parity-check codes that, for the first time, combines planar open-boundary layouts, finite-size advantages over surface codes, and syndrome extraction using only nearest-neighbour gates on a planar grid of qubits with either square or hexagonal connectivity. The resulting circuits achieve optimal constant-depth stabiliser measurement, independent of code size, and naturally remove leakage from the system by exchanging the roles of check and data qubits at each syndrome extraction round. We find finite-size instances such as a [[323,14,15]] code, whose code-efficiency ratio is nearly an order of magnitude larger than that of rotated surface-code patches. At around 40 circuit qubits per logical qubit, the best directional tile-code layouts reduce the per-logical per-round logical error rate by a factor of 100 relative to rotated surface-code memories. These results show that the advantages of quantum low-density parity-check codes can survive compilation into strictly planar nearest-neighbour circuits, bringing low-overhead fault-tolerant memories closer to near-term hardware.