Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
Guang Yang, Wei Zheng, Xiang Chen, Dong Liang, Peng Hu, Yukui Yang, Shaohang Peng, Zhenghan Li, Jiahui Feng, Xiao Wei, Kexin Sun, Deyuan Ma, Haotian Cheng, Yiheng Shen, Xing Hu, Terry Yue Zhuo, David Lo
cs.AR, cs.AI
Submitted: 2026-08-14
Updated: 2026-08-20
Comments: Accept in ACM Computing Surveys
Code: https://github.com/hkust-zhiyao/RTL-Coderhttps:
Project page: https://hdlbits.01xz.net/wiki/Main_Page
License: http://creativecommons.org/licenses/by/4.0/
The gist: Code generation has emerged as a critical research area at the intersection of Software Engineering (SE) and Artificial Intelligence (AI), attracting significant attention from both academia and
Terminology
Abstract
Code generation has emerged as a critical research area at the intersection of Software Engineering (SE) and Artificial Intelligence (AI), attracting significant attention from both academia and industry. Within this broader landscape, Verilog, as a representative hardware description language (HDL), plays a fundamental role in digital circuit design and verification, making its automated generation particularly significant for Electronic Design Automation (EDA). Consequently, recent research has increasingly focused on applying Large Language Models (LLMs) to Verilog code generation, particularly at the Register Transfer Level (RTL), exploring how these AI-driven techniques can be effectively integrated into hardware design workflows. Despite substantial research efforts have explored LLM applications in this domain, a comprehensive survey synthesizing these developments remains absent from the literature. This review fill addresses this gap by providing a systematic literature review of LLM-based methods for Verilog code generation, examining their effectiveness, limitations, and potential for advancing automated hardware design. The review encompasses research work from conferences and journals in the fields of SE, AI, and EDA, encompassing 70 papers published on venues, along with 32 high-quality preprint papers, bringing the total to 102 papers. By answering four key research questions, we aim to (1) identify the LLMs used for Verilog generation, (2) examine the datasets and metrics employed in evaluation, (3) categorize the techniques proposed for Verilog generation, and (4) analyze LLM alignment approaches for Verilog generation. Based on our findings, we have identified a series of limitations of existing studies. Finally, we have outlined a roadmap highlighting potential opportunities for future research endeavors in LLM-assisted hardware design.
Sources
- DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs
- RTL++: Graph-enhanced LLM for RTL Code Generation
- ASIC-Agent: An Autonomous Multi-Agent System for ASIC Design with Benchmark Evaluation
- DeepSeek LLM: Scaling Open-Source Language Models with Longtermism
- Evaluating LLMs for Hardware Design and Test
- VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation
- ChipGPT: How far are we from natural language hardware design
- Evaluating Large Language Models Trained on Code
- A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation
- Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS
- Abstractions-of-Thought: Intermediate Representations for LLM Reasoning in Hardware Design
- A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA
- From English to ASIC: Hardware Implementation with Large Language Model
- Textbooks Are All You Need
- DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learning
- DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligence
- EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code
- Assessing and Advancing Benchmarks for Evaluating Large Language Models in Software Engineering Tasks
- SecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chip
- Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction
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