Designing a Hybrid Digital / Analog Quantum Physics Emulator as Open Hardware

Introduction to the show: ident: Quantum Radio. Generated commentary on the latest quantum physics and condensed matter papers.

Kai: I'm Kai.

Mira: And I'm Mira, here with Lev.

Kai: We're looking at the paper: "Designing a Hybrid Digital / Analog Quantum Physics Emulator as Open Hardware".

Mira: Here's the gist of the paper. The gist Designing a Hybrid Digital/Analog Quantum Physics Emulator as Open Hardware introduces a new scheme for representing quantum information using analog signals to lessen bandwidth limitations in existing classical electronic hardware emulators.

Kai: This approach aims to achieve competitive performance against FPGA-based emulators by shifting the scaling problem from time and space to the precision and settling times of analog modules.

Mira: Naive Hardware Scaling Problem The naive approach involves mapping identification numbers for quantum states directly to a set of simple sinusoidal analog signals, where the complexity scales as: c = 2 · rank(M) + rank(W) − 1 (Page 3).

Kai: This yields an expression of the complexity C of a direct and purely hardwarebased implementation of a simplified state emulation that behaves in the way that K has been described (Page 3).

Paper summary: Kai: So we're looking at this paper, "Designing a Hybrid Digital / Analog Quantum Physics Emulator as Open Hardware". It looks like the main idea is they’re trying to fix the scaling issues in classical hardware emulators by using analog signals.

Mira: Yeah, they're proposing a way to represent quantum information using those analog signals that cuts down on the bandwidth limitations you see in current approaches in certain regimes <ref:2302.00821#pg1>.

Lev: It’s about taking full advantage of how analog signals can encode information using RMS voltage along with frequency and phase <ref:2302.00821#pg1>. I mean, the authors introduce a mathematical framework that separates the information needed for measurement in the computational basis from the stuff that isn't relevant to it <ref:2302.00821#pg1>.

Kai: And they build circuits that use this separation of concerns to simplify things when you're working with quantum information in this new representation <ref:2302.00821#pg1>. It sounds like they’re trying to make the process of working with these states much less complicated for the hardware <ref:2302.00821#pg1>.

Mira: The paper claims that it's comparatively very inexpensive, as low as a dollar and a half per qubit in some cases <ref:2302.00821#pg1>. They argue this approach can outmatch the computing capabilities of existing FPGA based emulators thirty-eight <ref:2302.00821#pg1,outmatch the computing capabilities of existing FPGA based emulators 38>.

Lev: But they also admit that scaling beyond tens of qubits is still impractical because of the constraints on analog hardware module precision <ref:2302.00821#pg76>. That's a big limitation for any real-world implementation, right?

Kai: Exactly. So what we’re hearing from this paper is that they are shifting the scaling problem away from time and space and towards the precision and settling times of analog modules <ref:2302.00821#pg35>. That’s a shift in focus for hardware development <ref:2302.00821#pg35>.

Mira: They start by looking at the naive approach where you map identification numbers for quantum states directly to simple sinusoidal analog signals, which scales with complexity C being three times two to the Q minus one, or three times two to the Q minus one <ref:2302.00821#pg3>. This shows how hard a direct implementation is in terms of hardware resources <ref:2302.00821#pg4>.

Lev: That complexity expression, C being three times two to the Q minus one, shows that directly simulating this simplified qubit state scales in hardware resources with O(two n) <ref:2302.00821#pg4>. That’s exponential scaling we’re trying to avoid <ref:2302.00821#pg4>.

Kai: Before this paper, the bandwidth limitation problem was a big one because representing an n qubit state with a complex oscillating time-domain signal means the number of qubits you can actually encode is limited by what the equipment can handle <ref:2302.00821#pg5>.

Paper summary: Mira: The La Cour and Ott scheme, for example, requires components like "two analog sources, two quadrature multiplier circuits, one phase shift circuit, and one bandpass filter" just to model a general single qubit state <ref:2302.00821#pg4>. That methodology scales with untenable complexity because it’s constrained by exponential scaling of required bandwidth <ref:2302.00821#pg5>.

Lev: So they propose this dual oscillator representation scheme to overcome those bandwidth limits, characterized by the property that a pair of oscillators must be sufficient to emulate n superimposed states <ref:2302.00821#pg6>. They use a probabilistic state with n observable values modeled by a probability simplex, and the Bloch sphere gives them a more true representation of a qubit state <ref:2302.00821#pg6>.

Kai: How do they break down the quantum state coefficients? The paper says each one is broken into three pieces: "Whether the coefficient is real or imaginary, Whether the coefficient is positive or negative, and The magnitude of the coefficient" <ref:2302.00821#pg7>. That seems like a pretty detailed way to handle it <ref:2302.00821#pg7>.

Mira: The core of this scheme involves mapping a set of quadratic relationships to a set of Cauchy sequences of angular values, which are then mapped to practically realizable frequencies <ref:2302.00821#pg10>. This measurable value is called the Higher Dimensional Observable, or HDO, because it’s a proxy for us to measure information in a higher dimensional space <ref:2302.00821#pg10>.

Lev: The HDO has to have n equal to two to the Q observable states, similar to the energy eigenstates of the quantum harmonic oscillator <ref:2302.00821#pg11>. The HDO shows up as a frequency, and its strength is equivalent to its probability of being consistently measured by a frequency measurement device <ref:2302.00821#pg12>.

Kai: So how does this translate into physical hardware? They utilize High Speed Analog Modules, or HSAMs, to convert parameters 'a' and 'g' into phi <ref:2302.00821#pg30>. These modules involve sequential steps like "setting the voltage V1, one half of the value of one in the desired numerical precision of the analog calculation module" <ref:2302.00821#pg35>.

Mira: The total time required to update a state is given by t tot equals one scalable time unit plus fifty nanoseconds plus Vxd minus delta minus Vxzero microsecond <ref:2302.00821#pg35>. And the speed of any quantum operation applied by this module is directly proportional to "the speed of the voltage sweep from Vx equal to Va to Vx equal to two times a minus one V1 over two" <ref:2302.00821#pg34>.

Lev: That speed relationship is key, it means how fast you can do an operation depends on the voltage sweep rate <ref:2302.00821#pg34>. They also encode the sign and phase information into the same signal as the probability distribution of a state’s observables by oscillating the frequency output omega from the AX7MAF1 high frequency oscillator <ref:2302.00821#pg36>.

Paper summary: Kai: That oscillation allows them to encode two to 2Q plus one separate phases in the frequency of the output oscillation, and this can be measured within a time frame between two to 2Q plus one over fifty megahertz and two to 2Q plus one over two point one gigahertz <ref:2302.00821#pg38>.

Mira: They also looked at an alternative hybrid analog digital approach where you apply operations to each ket individually using linear theory, which guarantees that when an operation multiplies the state by i, "a few things happen" <ref:2302.00821#pg40>. This involves swapping strengths between oscillator modules and updating the sign bit associated with the first part <ref:2302.00821#pg40>.

Lev: They use a Very Long Instruction Word, or VLIW architecture, to manage instruction scheduling, which separates digital and analog execution steps to keep the order of operations correct <ref:2302.00821#pg63>. That separation is important for making sure the quantum operations actually happen in sequence <ref:2302.00821#pg63>.

Kai: So what does this mean for practical use? The paper says the upper bound on representable qubits is Q equal to log of four million five hundred eighty thousand over log of two, which is twenty-two qubits with the AX7MAF1 <ref:2302.00821#pg41>. And the low-end cost per qubit is roughly one dollar and a half, while the high-end cost per qubit is approximately sixty three dollars and twenty five cents <ref:2302.00821#pg41>.

Mira: The paper concludes that this approach partially overcomes the exponential scaling issue by encoding information in an RMS voltage intermediately instead of a frequency, using the frequency domain only for encoding the phase component of the state <ref:2302.00821#pg76>. They say the frequencies used are derived via a mathematical framework inspired by the quantum harmonic oscillator to ensure they exist in a hierarchy that is optimal <ref:2302.00821#pg76>.

Lev: The main limitation they flag is that scaling beyond tens of qubits remains impractical because of constraints on analog hardware module precision <ref:2302.00821#pg76>. So, this scheme stops working where the analog hardware can't maintain the necessary accuracy for larger systems <ref:2302.00821#pg76>.

Kai: So, to sum up on "Designing a Hybrid Digital / Analog Quantum Physics Emulator as Open Hardware", they introduce a new way to use analog signals, using RMS voltage and frequency and phase <ref:2302.00821#pg1>. They separate the relevant measurement information from irrelevant information <ref:2302.00821#pg1>.

Mira: The implication is that it’s a relatively inexpensive way to compete with FPGA emulators, even if we can only realistically build systems up to about twenty two qubits <ref:2302.00821#pg41>. It opens up a new direction by focusing on improving analog electronic circuit performance <ref:2302.00821#pg76>.

Lev: So for the listener, it means that while we can't build huge quantum computers with this specific approach yet, the path forward might involve making those analog components more precise and faster <ref:2302.00821#pg76>. That's where real hardware improvements need to happen if we want to move past the NISQ regime <ref:2302.00821#pg76>.

Conclusion: Kai: So we’re wrapping up our look at this paper, "Designing a Hybrid Digital / Analog Quantum Physics Emulator as Open Hardware". Basically, they figured out a new way to handle quantum information using analog signals instead of just pure digital stuff.

Mira: Right. They took the scaling problem—that exponential explosion in required resources—and tried to move it somewhere else, away from time and space and toward how precise the analog hardware can actually be.

Lev: From my side, it’s interesting because they’re talking about circuits that use RMS voltage and frequency to represent states, which is a totally different kind of physical reality than what we usually build on FPGAs.

Kai: Yeah, I'm curious about the actual numbers they came up with. The paper claims this approach can be cheap enough to beat FPGA emulators in terms of performance per qubit, even if it’s not scalable for huge systems yet.

Mira: That’s what they say, and I think that’s the key point: you can get competitive results by focusing on better analog circuit design instead of just throwing more digital gates at a problem.

Lev: But the caveat is real, right? They explicitly state that scaling past tens of qubits is still out of reach because you run into precision limits in those analog modules.

Kai: So what does this mean for us building real quantum hardware? It suggests that improving the performance and settling times of analog components might be a more practical way to push the limits than just trying to invent bigger digital chips.

Mira: Exactly. It opens up a new avenue where classical simulators can improve by getting better at making those analog electronic circuits work correctly for quantum physics.

Lev: We need to see if we can translate that "improving analog circuit performance" idea into actual, measurable gains on real hardware platforms, not just theoretical models.