Peregrino: A Full-Hardware Accelerator for the Complete Falcon Post-Quantum Digital Signature Scheme on Resource-Constrained Edge Devices

arXiv:2609.31252 · cs.CR, cs.AR · Submitted 2026-09-25 · Read on arXiv

cs.CR, cs.AR

Submitted: 2026-09-25

Updated: 2026-09-25

Terminology

• Verification — 31× in this paper · explained in 2 episodes
• Core — 8× in this paper · explained in 2 episodes
• National Institute of Standards and Technology — 7× in this paper
• Edge Devices — 3× in this paper · explained in 2 episodes
• Fast Fourier Transform — 2× in this paper
• Floating-Point Unit — 2× in this paper
• Modular Architecture — 2× in this paper · explained in 4 episodes
• Adaptability — 1× in this paper · explained in 1 episode
• Adaptation — 1× in this paper · explained in 1 episode
• Digital Signature Algorithms — 1× in this paper
• Federal Information Processing Standards — 1× in this paper
• Hardware Description Language — 1× in this paper
• Number Theoretic Transform — 1× in this paper
• Trace — 1× in this paper · explained in 2 episodes
• Verifier — 1× in this paper · explained in 2 episodes

Sources

• How to factor 2048 bit RSA integers with less than a million noisy qubits
• Bi-SamplerZ: A Hardware-Efficient Gaussian Sampler Architecture for Quantum-Resistant Falcon Signatures

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