GRACIDIT: Graph-Circuit Digital Twin for Configuration-Induced Routing Delay Prediction in Zynq UltraScale+ FPGAs

arXiv:2609.30534 · eess.SY, cs.AR, cs.ET, cs.SY, eess.SP · Submitted 2026-09-24 · Read on arXiv

eess.SY, cs.AR, cs.ET, cs.SY, eess.SP

Submitted: 2026-09-24

Updated: 2026-09-24

Terminology

Calibration — 32× in this paper · explained in 7 episodes
Digital Twin — 15× in this paper · explained in 4 episodes
Accuracy — 6× in this paper · explained in 1 episode
Core — 6× in this paper · explained in 2 episodes
Benchmark — 5× in this paper · explained in 2 episodes
Redundancy — 4× in this paper · explained in 2 episodes
Generalization — 3× in this paper · explained in 13 episodes
Verification — 3× in this paper · explained in 2 episodes
Interpretability — 2× in this paper · explained in 15 episodes
Ablation — 1× in this paper · explained in 1 episode
Abstraction — 1× in this paper · explained in 1 episode
Adaptability — 1× in this paper · explained in 1 episode
Adaptation — 1× in this paper · explained in 1 episode
Additivity — 1× in this paper · explained in 1 episode
Aggregation — 1× in this paper · explained in 1 episode
Alignment — 1× in this paper · explained in 1 episode
Empirical Coverage — 1× in this paper · explained in 2 episodes
Failure Modes — 1× in this paper · explained in 3 episodes
International Symposium on FieldProgrammable Custom Computing Machines — 1× in this paper
Pruning — 1× in this paper · explained in 4 episodes
Regularization — 1× in this paper · explained in 3 episodes