RISC-V and machine learning: a survey
cs.LG, cs.AR
Submitted: 2026-09-17
Updated: 2026-09-17
Journal ref: The Journal of Supercomputing, 82(8):424, 2026
DOI: 10.1007/s11227-026-08463-z
Code: https://github.com/chipsalliance/rocket-chip
License: http://creativecommons.org/licenses/by-sa/4.0/
The gist: The intersection of open-source processor architectures and machine learning is driving the demand for customizable, efficient, and accessible hardware.
Terminology
Abstract
The intersection of open-source processor architectures and machine learning is driving the demand for customizable, efficient, and accessible hardware. This survey examines the state of the RISC-V ISA in machine learning applications, analyzing current capabilities, challenges, and future directions based on recent research. The analysis covers academic and commercial implementations, software frameworks, and real-world applications. The RISC-V machine learning ecosystem is evaluated, from instruction set extensions and core implementations to compiler optimizations and deployment strategies. Key contributions include a unified taxonomy of RISC-V ML implementations, a comparative analysis of performance and design trade-offs, an evaluation of software toolchain maturity, and the identification of emerging trends in instruction set extensions and specialized accelerators. Findings reveal progress in energy efficiency, specialized instruction development, and framework integration, while highlighting challenges in standardization, verification complexity, and ecosystem fragmentation. The analysis proposes four research directions to address current limitations: specialized neural processing extensions, adaptive and modular processor architectures, security frameworks, and energy-efficient multi-domain architectures. These directions provide a roadmap for advancing RISC-V as a foundational platform for next-generation machine learning systems.
Sources
- PCG: Mitigating Conflict-based Cache Side-channel Attacks with Prefetching
- A Survey on RISC-V Security: Hardware and Architecture
- Glow: Graph Lowering Compiler Techniques for Neural Networks
- Towards a high-performance AI compiler with upstream MLIR
- Composable and Modular Code Generation in MLIR: A Structured and Retargetable Approach to Tensor Compiler Construction
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