AI-Assisted Design of a Post-Quantum Cryptographic Accelerator: A Deployed-Silicon Case Study

arXiv:2609.04058 · cs.CR, cs.AR · Submitted 2026-09-03 · Read on arXiv

cs.CR, cs.AR

Submitted: 2026-09-03

Updated: 2026-09-03

License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/

Terminology

• Core — 26× in this paper · explained in 2 episodes
• Verification — 10× in this paper · explained in 2 episodes
• Benchmark — 4× in this paper · explained in 2 episodes
• Human-in-the-Loop — 4× in this paper · explained in 3 episodes
• Accuracy — 3× in this paper · explained in 1 episode
• Adam — 3× in this paper · explained in 2 episodes
• Benchmarking — 2× in this paper · explained in 3 episodes
• Agentic Loop — 1× in this paper · explained in 1 episode
• Generalizability — 1× in this paper · explained in 6 episodes
• International Symposium on Quality Electronic Design — 1× in this paper
• PCIe Function-Level Reset — 1× in this paper
• Redundancy — 1× in this paper · explained in 2 episodes
• Scaffolding — 1× in this paper · explained in 3 episodes
• Trace — 1× in this paper · explained in 2 episodes
• Verifier — 1× in this paper · explained in 2 episodes

Sources

• AutoChip: Automating HDL Generation Using LLM Feedback
• VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool
• MEIC: Re-thinking RTL Debug Automation using LLMs
• KiD: A Hardware Design Framework Targeting Unified NTT Multiplication for CRYSTALS-Kyber and CRYSTALS-Dilithium on FPGA
• ChipNeMo: Domain-Adapted LLMs for Chip Design
• QiMeng: Fully Automated Hardware and Software Design for Processor Chip
• SCAR: Power Side-Channel Analysis at RTL-Level

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