JENGA: Exploiting Counter-Based RowHammer Countermeasures to Break Real-Time Predictability

arXiv:2609.01077 · cs.CR, cs.AR · Submitted 2026-09-01 · Read on arXiv

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Introduction to the show: ident: AI Radio. Generated commentary on the latest Artificial Intelligence papers.

Tom: Next we'll be talking about the paper "JENGA: Exploiting Counter-Based RowHammer Countermeasures to Break Real-Time Predictability".

Jane: The paper was written by Valentin Abgrall, Marcello Traiola, Ruben Salvador, Maria Méndez Real, Alessandro Palumbo et al. from University of Rennes (Univ. Rennes) and CNRS (Centre National de la Recherche) and inria and CentraleSupélec and University of Bretagne-Sud (Univ. Bretagne-Sud).

Tom: Stay tuned as we take you through the paper and discuss its implications.

Jane: We also have Lu with us today — senior AI researcher at Tsinghua.

Tom: We also have Meng with us today — lead engineer at a mysterious AI startup.

Jane: We also have Lalam with us today — the in-house Large Language Model.

Tom: Alright, let's get started.

Summary of Findings: Tom: We just established how important timing is in real-time systems, so now we need to look closer at what the authors actually did.

Jane: They built this attack, J ENGA, by showing how an attacker can manipulate the internal state of a RowHammer countermeasure.

Lu: It’s not just random noise; they are deliberately engineering a specific state across multiple memory rows.

Meng: The goal is to set up what we're calling a J ENGA tower, which is essentially building up potential for failure.

Lalam: The analogy of the Jenga game perfectly captures how the system can be made unstable internally.

Tom: And once they execute that final move, it triggers a cascading series of mitigations that stall the memory subsystem.

Jane: That's where the "J ENGA tower" collapses, leading to massive delays in a victim task.

Lu: The core mechanism is when one alert causes N Refresh Management commands, and the neighboring rows are refreshed by those commands.

Meng: Because those newly refreshed neighbors have their counters incremented, they can trigger even more alerts.

Lalam: It’s a self-perpetuating cycle of forced downtime within the hardware itself.

Tom: The results are staggering, showing that J ENGA can delay tasks up to two hundred percent of their expected Worst-Case Execution Time.

Jane: That percentage is what makes this such a significant finding, showing the failure rate is much higher than anticipated.

Lu: This proves that even seemingly robust defenses like PRAC-N are susceptible to this systematic manipulation.

Meng: From an engineering standpoint, if we can't guarantee WCET because of a two hundred percent delay, the system is effectively unreliable for real-time use.

Lalam: We're discovering that hardware safeguards introduce new forms of timing instability that threaten our digital infrastructure.

Improvements and Implications: Tom: The findings are scary, but the paper doesn's just stop at showing the attack; they offer a path forward for safety-critical design.

Jane: They’ve developed a comprehensive analytical bound to account for these mitigation-induced delays in WCET analysis.

Lu: This is huge because traditional methods didn' not account for event-driven, cascading mitigations like this.

Meng: The authors have given us a formula that actually includes the worst-case impact of these RFM commands.

Lalam: It allows us to quantify the risk, which is a massive step towards designing more predictable systems.

Tom: We can now estimate C mitig, the contribution of mitigative actions, accurately in our calculations.

Jane: The methodology essentially incorporates the worst-case number of alerts and multiplies that by the worst-case latency of a single action.

Lu: This is vital for ensuring that when we design future real-time platforms, we are accounting for state manipulation.

Meng: It provides a clear framework for determining how much "buffer" time an application needs to survive the J ENGA attack.

Lalam: By incorporating these bounds, it forces us to change our culture of assuming hardware is static and unchanging.

Tom: The paper is offering a way to integrate deterministic counter-based countermeasures into WCET estimation.

Jane: It moves the discussion from just being about "if" an attack can happen to "how much" impact it will have, for every single task.

Lu: This analytical approach also provides bounds based on the physical size of a memory bank, which is very practical.

Meng: It’s a necessary evil; we have to design around this vulnerability rather than hoping it won't happen.

Lalam: We are forced to build systems that can tolerate this dynamic behavior as an accepted part of digital life.

Conclusion: Tom: So, we've covered how the J ENGA attack works and the analytical tools to counter its effect.

Jane: We've seen how it moves beyond just security into a critical area of timing predictability.

Lu: The entire process of manipulating those internal counters demonstrates that physical properties can be exploited by software logic.

Meng: It’s a comprehensive attack, and the fact that it's feasible in practice is a serious design challenge for engineers.

Lalam: We have to acknowledge this new vulnerability; we cannot ignore how hardware defenses can introduce timing risks.

Tom: The paper, "JENGA: Exploiting Counter-Based RowHammer Countermeasures to Break Real-Time Predictability," forces us to ask deeper questions about the reliability of modern memory.

Jane: It' is a wake-up call for everyone involved in designing safety-critical systems, emphasizing that security and timing are inextricably linked.

Lu: We must look at the physical architecture—the subarrays and banks—to truly understand where this vulnerability stops propagating.

Meng: Understanding the constraints on an attacker’s budget, or r attacker, is a practical step toward mitigating the risk.

Lalam: Our final thought is that this discovery pushes us toward a more robust and honestly predictable future digital culture.

Tom: Thanks to all our guests for sharing your insights!

Conclusion: Tom: Well, we've spent a lot of time today breaking down "JENGA: Exploiting Counter-Based RowHammer Countermeasures to Break Real-Time Predictability."

Jane: It’s clear that the implications of this paper are huge for safety-critical systems.

Lu: The discovery that counter statefulness can be exploited is a major theoretical advance in fault injection studies.

Meng: We need this information to redesign memory controllers and ensure we meet our WCET requirements, which the attack makes impossible under certain conditions.

Lalam: This paper has opened up a new conversation about how hardware defenses are, inherently, dynamic systems that can introduce timing vulnerabilities.

Tom: The findings show that the initial state of PRAC counters is so critical that it’s a serious design challenge.

Jane: We hope this research leads to more robust and predictable future designs for everyone in the industry.

Lu: We're excited to see how this knowledge will inform the next generation architectural standards.

Meng: I can already see the practical implications in hardware hardening protocols based on these constraints.

Lalam: Truly a groundbreaking paper that has profoundly impacted our understanding of digital reliability and stability.

Valentin Abgrall, Marcello Traiola, Ruben Salvador, Maria Méndez Real, Alessandro Palumbo, Angeliki Kritikakou

University of Rennes (Univ. Rennes) · CNRS (Centre National de la Recherche) · inria · CentraleSupélec · University of Bretagne-Sud (Univ. Bretagne-Sud)

cs.CR, cs.AR

Submitted: 2026-09-01

Updated: 2026-09-01

Comments: To appear at the 47th IEEE Symposium on Real-Time Systems (RTSS) 2026, 14 pages, 11 figures, 1 table

License: http://creativecommons.org/licenses/by/4.0/

Importance score: 80/100

The gist: I apologize, but the actual content of the arXiv paper titled "JENGA: Exploiting Counter-Based RowHammer Countermeasures to Break Real-Time Predictability" was not provided.

Key concepts

JENGA Attack: This attack demonstrates how an adversary can manipulate the internal state of a RowHammer countermeasure. By engineering specific states across memory rows, it triggers a self-perpetuating cycle of forced downtime, leading to massive delays in system tasks.
Worst-Case Execution Time (WCET): WCET is the maximum amount of time a task is expected to take. The JENGA attack showed that hardware safeguards can introduce timing instability, causing delays up to two hundred percent of the expected WCET, making systems unreliable for real-time use.
Mitigation-Induced Delays: These are timing delays caused by the hardware's own defenses (countermeasures). The paper shows that these defensive actions are dynamic and can introduce new forms of instability, which must be factored into future predictable system designs.

Terminology

Core — 16× in this paper · explained in 2 episodes
Memory Controller — 13× in this paper
Benchmark — 11× in this paper · explained in 2 episodes
Worst-Case Execution Time — 6× in this paper
International Symposium on Computer Architecture — 4× in this paper
IEEE Symposium on Security and Privacy — 3× in this paper
Redundancy — 2× in this paper · explained in 2 episodes
Abstraction — 1× in this paper · explained in 1 episode
Commentary — 1× in this paper · explained in 2 episodes

Summary

I apologize, but the actual content of the arXiv paper titled JENGA: Exploiting Counter-Based RowHammer Countermeasures to Break Real-Time Predictability was not provided. To fulfill your request—which requires extracting specific details, quoting key phrases, and adhering to a strict word count and structure—I must have the text of the paper itself.

Please provide the full text of the arXiv paper, and I will immediately generate a summary that meets all your exacting standards: one orienting paragraph, 3 to 5 bolded sections with detailed paragraphs, appropriate lists, and precise adherence to quoted material, ensuring no commentary or external information is included.

Improvements for AI systems

(Self-Correction/Internal Monologue: The provided bibliography is not a single paper but a collection of highly specialized works focused on Hardware Architecture, Real-Time Systems, and Memory Timing Analysis. My role is to bridge this gap. AI systems traditionally assume ideal, predictable compute time. These papers prove that real-world timing is dominated by non-deterministic memory behavior. Therefore, the core improvement must be moving AI from theoretical performance metrics (FLOPS) to guaranteed, worst-case timing metrics (WCET) in resource-constrained environments.)

Improvement: Integrate dynamic memory bandwidth reservation and explicit task partitioning mechanisms (drawing from [42] and [53]). The AI inference pipeline must be re-architected to treat DRAM access not as a shared pool, but as a resource governed by strict Quality of Service (QoS) guarantees. This involves profiling the memory access patterns of the model's weights and intermediate activations a priori to predict contention hotspots.
Improved AI System Capability: The system can provide guaranteed maximum latency bounds for inference, even when running alongside non-critical background tasks (e.g., sensor data logging or network communication). This is critical for safety-critical applications (autonomous vehicles, medical monitoring) where timing jitter is unacceptable.
Improvement: Implement a mandatory, cycle-accurate simulation layer that replaces standard compiler assumptions. This layer must utilize advanced DRAM simulators (like Ramulator 2.0 [48]) and architectural emulators (like gem5 [47]) to model the full memory hierarchy, including refresh cycles ([43], [44]), row/bank conflicts, and cache misses in a heterogeneous MPSoC context. This moves timing analysis from generalized models to physical hardware fidelity.
Improved AI System Capability: The system can verify timing constraints virtually before deployment on the target hardware. Developers receive precise reports detailing potential latency spikes caused by specific memory access sequences, allowing for model restructuring (e.g., reordering layers or changing data layouts) to eliminate non-deterministic bottlenecks.
Improvement: Introduce a software-defined layer that monitors and mitigates transient hardware faults and physical interference (Drawing from [45] and [51]). This involves incorporating techniques like redundancy checks or dynamic scheduling adjustments when the system detects evidence of high memory contention or predicted soft errors (e.g., during DRAM refresh cycles).
Improved AI System Capability: The AI inference remains robustly reliable even under adverse operating conditions (high thermal load, electrical noise, minor hardware degradation). It can gracefully degrade its performance or switch to a redundant computation path rather than failing catastrophically when a timing violation or transient fault occurs.
Improvement: The model quantization and pruning process must be explicitly guided by detailed microarchitectural characterization data (drawing from [52]). Instead of simply minimizing model size, the optimization routine must minimize memory bandwidth usage and DRAM access complexity. This means restructuring the AI model to favor data reuse within local caches (SRAM) and avoid patterns known to cause high bank conflict rates.
Improved AI System Capability: The system achieves optimal energy efficiency and throughput on specific, resource-constrained edge hardware. It guarantees that the computational load fits within the predicted memory bandwidth budget of the target chip, maximizing operational time while maintaining required accuracy thresholds.

Abstract

Safety-critical real-time systems must satisfy multiple dependability requirements, notably time predictability and security. In such systems, tasks must complete within bounded and known execution times, typically characterised through Worst-Case Execution Time (WCET) analysis. At the same time, DRAM-based platforms are increasingly sensitive to the RowHammer read-disturbance security vulnerability, which has motivated the development of numerous hardware and software countermeasures in both academia and industry. However, the impact of these defences is generally evaluated in terms of average-case performance, a metric that is insufficient for safetycritical real-time systems, where worst-case behaviour is the primary concern. In this paper, we study the impact of RowHammer countermeasures based on hardware counters on the timing behaviour of real-time systems. We use a Per-Row-Activation-Counter (PRAC) countermeasure as a case study, standardised for recent DDR5 memories, and show that it can introduce significant timing variations. Based on this observation, we introduce JENGA, an attack in which an attacker-controlled task manipulates the internal state of the RowHammer countermeasure mechanism to increase the execution time of a victim real-time task beyond its expected WCET. We implement JENGA in a gem5 and Ramulator 2.0 simulation environment and evaluate its impact on TACLeBench workloads. We show that such an attack can delay tasks up to 200% of their WCET, making the initial timesafety assumptions unsafe. To address this issue, we derive a safe analytical bound that accounts for mitigation-induced delays in WCET analysis for DRAM systems protected by hardware countermeasures, such as PRAC-N.