SoK: ARCUS: On the Efficiency and Efficacy of Hardware Fuzzing

arXiv:2608.23933 · cs.CR, cs.SE · Submitted 2026-08-25 · Read on arXiv

cs.CR, cs.SE

Submitted: 2026-08-25

Updated: 2026-08-25

Code: https://github.com/riscv-software-src/riscv-tests

Project page: https://google.github.io/oss-fuzz

License: http://creativecommons.org/licenses/by/4.0/

The gist: This work presents a comprehensive analysis of contemporary hardware fuzzing techniques applied across three major abstraction layers: Instruction Set Architecture (ISA), microarchitecture, and

Terminology

Abstract

This work presents a comprehensive analysis of contemporary hardware fuzzing techniques applied across three major abstraction layers: Instruction Set Architecture (ISA), microarchitecture, and Register-Transfer Level (RTL). Our study examines key factors including input stimulus quality, mutation strategies, feedback mechanisms, target platforms, reference models, and achieved coverage. We find challenges, goals, and design trade-offs vary significantly across abstraction layers. We further identify several unmet needs in current hardware fuzzing practices, such as intelligent input generation, reliable and scalable golden reference models, expressive feedback channels, and cross-layer integration. Building on these insights, we outline future research directions, including hybrid fuzzing frameworks, AI-assisted test generation, scalable reference models, standardized evaluation metrics and benchmarks, and human-in-the-loop automation for guided exploration and analysis. Together, they aim to unlock efficient, reliable, and comprehensive hardware verification solutions.

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