AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models

AaLLM is an open-source, end-to-end multi-agent LLM workflow for analog circuit design that takes user specifications as input and outputs the appropriate netlist, encompassing both topology generation and circuit sizing. The framework automates the creation of a relevant knowledge base from research papers and textbooks to combat tedious manual data collection, and implements a Retrieval Augmented Generation (RAG) model to emulate circuit design expertise using this knowledge base. AaLLM uses a novel tri-agent feedback system comprising a Designer that determines circuit component values, a Critic that scrutinizes these values, and an Evaluator that minimizes circuit sizing iterations by arbitrating between the other two agents. Additionally, AaLLM generates novel, valid topologies by leveraging a fine-tuned Sequence-to-Sequence (Seq2Seq) model that learns the effect of each connection in conventional topologies and recombines them to form new circuits.

The framework decomposes the analog design problem into two complementary stages handled by different types of LLMs: a fine-tuned generative model for topology generation, and a multi-agent reasoning system for circuit sizing. Both stages are supported by the RAG module that draws on established circuit theory from an analog design knowledge base. AaLLM represents every circuit as a bipartite component-node matrix rather than a free-form SPICE netlist or a directed graph, which decouples topology from sizing and provides a fixed-length token structure that the transformer decoder can generate under position-aware constraints.

The topology generator maps the resolved target spec to a set of candidate circuit structures, formulated as a conditional Sequence-to-Sequence problem learning the mapping from performance specs to bipartite matrices. The model is a fine-tuned FLAN-T5 encoder-decoder, chosen for its encoder-decoder split, instruction-tuned pre-training, and span corruption objective that aligns with the fill-in-the-blank structure of the task. Training follows a three-stage curriculum that gradually exposes the model to harder versions of the task. For each input spec, AaLLM produces multiple candidate topologies, giving the downstream selection stage a diverse pool to choose from.

The RAG module injects reasoning by letting an LLM selection agent consult an analog-design knowledge base before selecting a topology, issuing a query that is searched against two separate indexes: one matching by semantics and one matching by exact keywords, with results merged using weighted reciprocal-rank fusion. A distinctive feature of the knowledge base construction is contextual augmentation, where each raw text chunk is passed through an LLM to create a short description situating the chunk within its corresponding document.

For circuit sizing, AaLLM employs three specialized LLM agents (Evaluator, Critic, and Designer) operating in a closed loop around a SPICE simulator. The Critic receives the current SPICE result and target spec, producing a structured diagnosis with severity status and the subset of components most directly responsible for failure. The Evaluator monitors the trajectory over recent iterations, catching patterns that no single diagnosis can detect, and instructs the Designer either to follow a specific action, temporarily ban certain circuit parameters from being modified, or override the current optimization strategy. The Designer is the only agent that actually touches parameters, emitting a small list of modifications specifying a component, parameter, action, and value.

The curriculum controller enforces a process flow mimicking how a human designer would approach the problem, proceeding through three sequential phases: DC biasing, AC analysis, and finally transient analysis. Each phase is promoted only when its objectives are met, and later phases run background checks that can demote the loop if earlier objectives regress beyond relaxed tolerances.

AaLLM-generated novel topologies achieve a figure of merit (FoM) comparable to that of known topologies, and up to 3x higher for certain circuits. Testing on several circuit topologies, results show a 3x - 4.5x decrease in the number of SPICE calls at inference when compared to state-of-the-art multi-agent LLM pipelines, and a 40x decrease in wall-clock time compared to State-Of-The-Art approaches. The tri-agent sizing loop meets the target specs in 91.6% of cases across a test bench spanning a wide range of design specs. On the direct AnaFlow benchmark, AaLLM meets the target specs while calling SPICE twice, compared to AnaFlow's 9 SPICE calls, showing a 4.5x decrease in number of SPICE calls and a 40x decrease in wall-clock time. Against Atelier, AaLLM meets the target specs on all 8 circuits where Atelier meets only 4, using 2.79x fewer circuit simulations. The ablation study shows the full AaLLM configuration improves UGB by 73% while reducing the iteration count by 40% compared to variants without RAG, physics heuristics, or matching constraints. AaLLM achieves Pass@1 = 100% for both structural and electrical validity on all 24 target specs in the OPAMP benchmark suite, and successfully sizes active filters across three topologies (Sallen-Key low-pass, Sallen-Key high-pass, and multi-feedback band-pass) to meet all target specs.

Improvements to AI Systems:

1. Implement a Tri-Agent Arbitration Loop for Iterative Design Tasks

• Add three specialized agents: a Designer (proposes concrete parameter changes), a Critic (diagnoses failures against target specs with severity and component attribution), and an Evaluator (monitors multi-step trajectory to detect systemic patterns, issue bans on specific parameters, or override strategy).

• The improved AI system can solve complex, multi-constraint optimization problems (e.g., circuit sizing, hyperparameter tuning, structural engineering) with fewer iterations, by catching cross-step failures that single-step feedback misses.

2. Use a Curriculum Controller with Phase Gating and Regression Checks

• Decompose a complex task into sequential phases (e.g., DC biasing → AC analysis → transient analysis). Promote to the next phase only when current objectives are met, and run background checks that demote the loop if earlier objectives regress beyond relaxed tolerances.

• The improved AI system can handle multi-stage engineering workflows (e.g., chip design, robotics control, drug synthesis) where later stages depend on earlier ones, preventing cascading failures and ensuring robustness.

3. Adopt Bipartite Component-Node Matrix Representation for Structured Generation

• Represent any system as a fixed-length bipartite matrix (components vs. nodes) instead of free-form text or graphs. This decouples topology from sizing and enables position-aware constraint generation.

• The improved AI system can generate novel, valid structures (e.g., circuits, neural architectures, metabolic pathways) with guaranteed structural validity, and can be trained more efficiently due to fixed-length tokenization.

4. Integrate Retrieval-Augmented Generation (RAG) with Dual-Index Search and Contextual Augmentation

• Build a knowledge base from raw documents by passing each chunk through an LLM to create a short situational description. At inference, query two indexes (semantic + exact keyword) and merge results via weighted reciprocal-rank fusion.

• The improved AI system can reason with domain-specific knowledge (e.g., analog design, legal precedents, medical guidelines) more accurately, reducing hallucinations and improving decision quality, especially in niche fields.

5. Fine-Tune a Seq2Seq Model with Three-Stage Curriculum Learning for Topology Generation

• Use an encoder-decoder model (e.g., FLAN-T5) with span corruption objective, trained progressively: first on simple mappings, then on harder ones with partial constraints, finally on full spec-to-topology mapping.

• The improved AI system can generate diverse, novel solutions from high-level specifications (e.g., low-power amplifier → multiple candidate circuit topologies) with high Pass@1 validity, enabling creative design exploration.

6. Decouple Generation from Sizing via Separate LLM Stages

• Split the problem into (a) a generative model for structure/topology and (b) a multi-agent reasoning system for parameter optimization, both supported by the same RAG module.

• The improved AI system can handle problems where structure and parameters are interdependent but require different reasoning modes—e.g., designing a chemical reactor (topology) and then optimizing its operating conditions (sizing)—without cross-contamination of errors.

7. Implement Physics/Heuristic-Informed Constraints in the Sizing Loop

• Inject domain rules (e.g., transistor operating regions, Kirchhoff's laws) as hard constraints or bans on parameter modifications, guided by the Evaluator agent.

• The improved AI system can avoid physically invalid or practically infeasible solutions, reducing wasted simulation calls and improving convergence speed (e.g., 40x wall-clock reduction).

8. Use Weighted Reciprocal-Rank Fusion for Multi-Source Retrieval

• When combining semantic and keyword search results, apply weighted reciprocal-rank fusion to prioritize highly relevant chunks from either source.

• The improved AI system can answer queries that require both conceptual understanding and exact terminology (e.g., design a band-pass filter with 3dB ripple) more reliably, improving downstream reasoning accuracy.

What the Improved AI System Can Do:

• Automatically design novel, valid analog circuits (or analogous engineering artifacts) from user specs, matching or exceeding human-expert performance (e.g., 3x higher figure of merit).

• Optimize complex systems with 3–4.5x fewer simulation/iteration calls and 40x faster wall-clock time than prior state-of-the-art, by combining multi-agent arbitration, curriculum control, and physics-informed constraints.

• Generate diverse candidate topologies with 100% structural and electrical validity, then size them to meet target specs in 91.6% of cases across a wide benchmark range.

• Transfer to other domains: e.g., automated VLSI layout, control system design, synthetic biology pathway construction, or even multi-stage business process optimization—wherever structure generation and parameter tuning are separable and iterative feedback is available.