CHARGE: Leveraging CWE Hierarchies for Hardware Security SystemVerilog Assertion Generation

arXiv:2607.27776 · cs.CR · Submitted 2026-07-30 · Read on arXiv

Xiao Tan, Cynthia Sturton

cs.CR

Submitted: 2026-07-30

Comments: This paper is an extended version of the paper accepted to the IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2026)

Code: https://github.com/HWSecUNC/CHARGE

License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/

Terminology

• Verification — 50× in this paper · explained in 2 episodes
• Benchmark — 24× in this paper · explained in 2 episodes
• Core — 8× in this paper · explained in 2 episodes
• Trace — 7× in this paper · explained in 2 episodes
• Abstraction — 6× in this paper · explained in 1 episode
• Accuracy — 6× in this paper · explained in 1 episode
• Common Weakness Enumeration — 4× in this paper
• Fine-Tuning — 3× in this paper · explained in 5 episodes
• Formal Verification — 3× in this paper · explained in 2 episodes
• Large Language Models (LLMs) — 2× in this paper · explained in 6 episodes
• Prompt Engineering — 2× in this paper · explained in 4 episodes
• Failure Modes — 1× in this paper · explained in 3 episodes
• Formal Methods — 1× in this paper · explained in 3 episodes
• Generalization — 1× in this paper · explained in 13 episodes
• Hardware Oriented Security and Trust — 1× in this paper
• Iterative Refinement — 1× in this paper · explained in 3 episodes
• alpha — 1× in this paper · explained in 1 episode

Sources

• DIVAS: An LLM-based End-to-End Framework for SoC Security Analysis and Policy-based Protection
• AKER: A Design and Verification Framework for Safe andSecure SoC Access Control
• FLAG: Formal and LLM-assisted SVA Generation for Formal Specifications of On-Chip Communication Protocols
• Assertain: Automated Security Assertion Generation Using Large Language Models
• LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs
• AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs
• SVAgent: AI Agent for Hardware Security Verification Assertion
• LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verification
• Unlocking Hardware Security Assurance: The Potential of LLMs

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