GNN-based Path-aware multi-view Circuit Learning for Technology Mapping

arXiv:2601.14286 · cs.ET, cs.LG · Submitted 2026-01-14 · Read on arXiv

cs.ET, cs.LG

Submitted: 2026-01-14

Updated: 2026-09-19

Comments: Withdrawn by the authors because the manuscript was posted prematurely and requires substantial revision before further dissemination

License: http://creativecommons.org/licenses/by/4.0/

The gist: Traditional technology mapping suffers from systemic inaccuracies in delay estimation due to its reliance on abstract, technology-agnostic delay models that fail to capture the nuanced timing

Terminology

Abstract

Traditional technology mapping suffers from systemic inaccuracies in delay estimation due to its reliance on abstract, technology-agnostic delay models that fail to capture the nuanced timing behavior behavior of real post-mapping circuits. To address this fundamental limitation, we introduce GPA(graph neural network (GNN)-based Path-Aware multi-view circuit learning), a novel GNN framework that learns precise, data-driven delay predictions by synergistically fusing three complementary views of circuit structure: And-Inverter Graphs (AIGs)-based functional encoding, post-mapping technology emphasizes critical timing paths. Trained exclusively on real cell delays extracted from critical paths of industrial-grade post-mapping netlists, GPA learns to classify cut delays with unprecedented accuracy, directly informing smarter mapping decisions. Evaluated on the 19 EPFL combinational benchmarks, GPA achieves 19.9%, 2.1% and 4.1% average delay reduction over the conventional heuristics methods (techmap, MCH) and the prior state-of-the-art ML-based approach SLAP, respectively-without compromising area efficiency.

Sources

Related papers