Modelling the Impact of Device Imperfections on Electron Shuttling in SiMOS devices

arXiv:2512.03853 · quant-ph, cond-mat.mes-hall · Submitted 2025-12-03 · Read on arXiv

quant-ph, cond-mat.mes-hall

Submitted: 2025-12-03

Updated: 2026-09-23

Terminology

• Fidelity — 31× in this paper · explained in 2 episodes
• Accuracy — 5× in this paper · explained in 1 episode
• Robustness — 3× in this paper · explained in 5 episodes
• Valley Splitting — 3× in this paper · explained in 2 episodes
• Benchmark — 2× in this paper · explained in 2 episodes
• Ab Initio — 1× in this paper · explained in 1 episode
• All-to-All Connectivity — 1× in this paper · explained in 1 episode
• Anisotropy — 1× in this paper · explained in 3 episodes
• Hilbert Space — 1× in this paper · explained in 2 episodes
• IEEE International Electron Devices Meeting — 1× in this paper

Sources

• A superinductor in a deep sub-micron integrated circuit
• Spin Readout in a 22 nm Node Integrated Circuit
• A trilinear quantum dot architecture for semiconductor spin qubits
• Mapping g-factors and complex intervalley coupling in Si/SiGe by conveyor-mode shuttling
• Weight-four parity checks with silicon spin qubits
• Numerical simulation of coherent spin-shuttling in a QuBus with charged defects
• Constraints on Atomistic Disorder for Scalable Electron Spin Shuttling

Related papers

• Reconquering Bell sampling on qudits: stabilizer learning and testing, quantum pseudorandomness bounds, and more
• Encrypted clones can leak: Classification of informative subsets in Quantum Encrypted Cloning
• Polynomial-time classical and quantum simulation of quantum impurity models
• Theory of quantum-enhanced interferometry with general Markovian light sources
• A convergent hierarchy of spectral gap certificates for qubit Hamiltonians
• Universal Bound and Phase Transition in Many-Body Fermionic Non-Gaussianity