A 16.28 ppm/ C Temperature Coefficient, 0.5V Low-Voltage CMOS Voltage Reference with Curvature Compensation

arXiv:2508.15729 · eess.SY, cs.SY · Submitted 2025-08-21 · Read on arXiv

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Introduction to the show: ident: Robotics Radio. Generated commentary on the latest robotics and control papers.

Rosa: Today's paper: "A 16.28 ppm/ C Temperature Coefficient, 0.5V Low-Voltage CMOS Voltage Reference with Curvature Compensation".

Dev: This paper presents a fully-integrated CMOS voltage reference designed in a 90 nm process node that achieves an excellent temperature coefficient, low line sensitivity,

Rosa: First, who's behind it and why it matters.

Paper summary: Dev: So, looking at the "A sixteen point two eight ppm/ C Temperature Coefficient, 0 point 5V Low-Voltage CMOS Voltage Reference with Curvature Compensation," the authors' main achievement is delivering that specific temperature coefficient of sixteen point two eight ppm/°C while operating at such a low supply voltage of zero point five V <ref:2508.15729#pg0>.

Rosa: And the authors managed to do this by using a combination of PTAT, CTAT, and curvature-correction currents for mutual compensation across different MOSFETs <ref:2508.15729#pg0>. It seems like they’ve successfully engineered a solution that maintains remarkable stability over the entire range from-forty °C to one hundred thirty °C <ref:2508.15729#pg0>.

Taro: From an autonomy research standpoint, this means we have a reference voltage source that doesn't drift significantly when deployed in unpredictable external conditions, which is crucial for systems that need consistent power levels for their sensors and processing units <ref:2508.15729#pg0>.

Dev: I think the implication here is that we can design more efficient, low-power control systems where the reference voltage doesn't become a major source of error due to environmental temperature fluctuations or low supply voltages <ref:2508.15729#pg0>.

Rosa: That efficiency combined with stability opens up avenues for deploying these types of reference circuits in edge devices that need to operate reliably in varied conditions, which is what I'm looking at for field robotics <ref:2508.15729#pg0>.

Taro: The real impact could be on creating more resilient autonomous agents capable of surviving and operating effectively outside of highly controlled laboratory settings <ref:2508.15729#pg0>.

Dev: We also have to consider the power efficiency aspect, which they report at zero point six seven µW at zero point five V, suggesting that these low-voltage applications can be very power-conscious while still maintaining good performance <ref:2508.15729#pg0>.

Rosa: So, in simple terms, this paper presents a highly stable voltage reference that runs on very little power and stays accurate across a wide temperature range, which is what makes it relevant for robust field applications <ref:2508.15729#pg0>.

Conclusion: Rosa: So, to wrap up this discussion on "A sixteen point two eight ppm/ C Temperature Coefficient, zero point 5V Low-Voltage CMOS Voltage Reference with Curvature Compensation," we've seen how they managed to pack this level of precision into such a compact design running on just half a volt <ref:2508.15729#pg2>.

Dev: Exactly; the key takeaway is that achieving such high stability at these low supply voltages isn't just about squeezing the voltage down; it’s about intelligently compensating for the temperature changes that usually wreck those circuits.

Taro: And from an autonomy standpoint, having a reference voltage that maintains this accuracy across extreme temperatures means our navigation systems or sensor calibrations won't suddenly lose sync when we go into deep cold or intense heat.

Rosa: Right, and thinking about real-world deployment, does this stability translate to long operational time for a field robot before we need to recalibrate?

Dev: We’ve looked at the power consumption figures, and they report keeping that reference voltage within one percent of its target even when the operating environment swings wildly from minus forty degrees Celsius up to one hundred thirty.

Taro: If the system can handle those thermal stresses without significant drift, it opens up possibilities for autonomous agents operating in environments we haven't fully mapped yet.

Rosa: It really feels like we’re getting a solid foundation for more reliable hardware that doesn't need constant on-site adjustments, which is what field robotics demands.

Dev: The circuit design itself relies on careful mutual compensation between the PTAT and CTAT elements to counteract thermal drift, which is a neat engineering feat in CMOS technology.

Taro: What I find particularly interesting is how this approach addresses the uncertainty that comes with unpredictable external conditions in autonomous systems.

Rosa: It makes me wonder if we can use this kind of robust reference across multiple subsystems on a single platform for even better overall reliability.

Birla Institute of Technology and Science

eess.SY, cs.SY

Submitted: 2025-08-21

Updated: 2026-10-05

Comments: 6 pages, 29th International Symposium on VLSI Design and Test (VDAT 2025)

License: http://creativecommons.org/licenses/by/4.0/

Importance score: 86/100

The gist: This paper presents a fully-integrated CMOS voltage reference designed in a 90 nm process node that achieves an excellent temperature coefficient, low line sensitivity, and power efficiency at a very

Key concepts

PTAT Circuit: The Proportional to Absolute Temperature (PTAT) circuit uses two MOSFETs operating in subthreshold. Its current is proportional to the absolute temperature, allowing the circuit to generate a voltage that remains stable even when the ambient temperature changes significantly. This improves power efficiency by mimicking BJT characteristics.
CTAT Circuit: The Complementary to Absolute Temperature (CTAT) architecture exploits multi-threshold MOS transistor characteristics. It generates a voltage component that is complementary to the absolute temperature change, helping to further stabilize the output reference voltage across varying temperatures.
Curvature Compensation: This technique uses an additional transistor placed in parallel with a resistor to exploit the exponential-like temperature dependence of leakage current. By adjusting this component, the design can extend its stable operating range and improve the overall accuracy of the temperature coefficient performance.

Terminology

Core — 6× in this paper · explained in 2 episodes
Accuracy — 1× in this paper · explained in 1 episode
Calibration — 1× in this paper · explained in 7 episodes
Edge Devices — 1× in this paper · explained in 2 episodes

Summary

This paper presents a fully-integrated CMOS voltage reference designed in a 90 nm process node that achieves an excellent temperature coefficient, low line sensitivity, and power efficiency at a very low operating supply voltage. The proposed design leverages subthreshold operation and near-weak inversion characteristics of MOSFETs to generate a stable reference voltage with remarkable stability across wide temperature variations.

Architecture Overview

The circuit is a purely CMOS-based voltage reference architecture that utilizes the mutual compensation of three current sources to achieve temperature invariance. The core design incorporates PTAT (proportional to absolute temperature), CTAT (complementary to absolute temperature), and curvature-correction currents. This combination allows the circuit to maintain stability over a wide range from-40 °C to 130 °C. The design is optimized for low operating supply voltage, targeting an operating voltage of 0.5 V, while maintaining good power efficiency, consuming only 0.67 µW at this supply level.

PTAT Circuit Implementation

The PTAT circuit core consists of two MOSFETs, M1 and M2, which operate in the subthreshold region and exhibit I-V characteristics similar to a BJT, leading to improved power efficiency. The aspect ratios are set such that M2 is Np times larger than M1. The leakage currents of these transistors are defined by equation (1), which depends on the subthreshold operation:

**"Ids = Ids0e / (Vgs−Vth) **

This allows the PTAT current to be derived, where the final expression for Iptat is given as:

**"Iptat = nvT / R1 **

The strength and slope of this PTAT current are adjustable by altering Np or the ratio of the sizes of M1 and M2, and R1.

CTAT Circuit Implementation

The CTAT architecture is a modified version exploiting the multi-threshold characteristics of a MOS transistor, utilizing the Unified Current Control Model (UICM). The core component is MOSFET M0, which is diode connected and operates mostly in forward saturation. The drain current ID for M0 can be given by:

ID = ISif / if ⇒ if = ID / IS (Equation 6) where 'if' represents the forward inversion level. This behavior is used to generate a CTAT voltage, Vctat, which is replicated across resistor R2 with an Nc times higher current as compared to M0 drain current. The required width-to-length ratio of M0 is derived from equation (11):

Curvature Compensation

To enhance the temperature coefficient performance and extend the operational temperature range, curvature compensation is employed. This technique exploits the exponential-like property of subthreshold leakage current with respect to temperature, as seen in Fig. 4. A transistor M7 is placed in parallel to R3 such that it drains out current exponentially as temperature increases, thereby decreasing the output reference voltage across R3 and reducing the overall temperature deviation. The strength of this compensation can be easily adjusted by varying the aspect ratio of M7.

Output Reference Generator

The final output voltage generator circuit is realized using cascode current mirrors to enhance its current mirroring capabilities, which improves line sensitivity and power supply rejection. The PTAT and CTAT currents are mirrored and summed to the output branch by ratios of αp and αc respectively, through resistor R3. The resulting reference voltage is given by:

VREF = R3(αpIptat + αcIctat − Icomp) (Equation 13) The circuit was designed to produce a reference voltage of 205 mV. By carefully choosing the strengths of PTAT, CTAT, and curvature compensation, the proposed circuit achieves a brilliant temperature coefficient of 16.28 ppm/°C with a maximum deviation of just 0.57 mV or 570 µV. The resulting performance summary shows a reference voltage of 204.85 mV with a temperature coefficient of 16.28 ppm/°C in the wide range of-40 °C to 130 °C, consuming just 0.67 µW at a 0.5 V supply and 1.3 µW at a 1 V supply."

Performance Summary

The circuit demonstrates an excellent temperature coefficient of 16.28 ppm/°C, with a line sensitivity of just 1.65 %/V, and a power supply rejection ratio (PSRR) of -50 dB at 10 kHz when equipped with cascode modification. The reference voltage reaches its nominal value of 205 mV (with less than 1% error) for a tremendously low minimum supply voltage of 0.5 V, confirming the design's suitability for low-voltage applications.

Improvements for AI systems

Here are the specific improvements to AI systems that could be made by leveraging this CMOS voltage reference design:

The proposed voltage reference enables ultra-low-voltage operation (down to 0.5V) for critical analog front-ends in AI accelerators and edge devices, leading to significant power savings compared to traditional bandgap references that require higher supply voltages.
This low-voltage capability allows for the deployment of highly energy-efficient Analog-to-Digital Converters (ADCs) and sensors within AI inference hardware, enabling smaller, more power-constrained IoT and wearable AI devices.
The exceptionally low temperature coefficient (16.28 ppm/°C) ensures high accuracy in the voltage reference output across extreme operating environments (-40°C to 130°C), which is vital for maintaining stable precision in neural network training and inference hardware deployed in diverse climates or industrial settings.
The improved power efficiency (as low as 0.67 µW) allows AI systems to operate on harvested energy sources (e.g., battery-powered edge devices) for longer periods, extending the operational life of autonomous systems and IoT sensors without requiring frequent recharging.
The enhanced Line Sensitivity (1.65%/V) allows for more precise voltage scaling in digital-analog interfaces, enabling finer control over signal conditioning stages in AI hardware that interface with external sensors or memory components.

Abstract

This paper presents a fully-integrated CMOS voltage reference designed in a 90 nm process node using low voltage threshold (LVT) transistor models. The voltage reference leverages subthreshold operation and near-weak inversion characteristics, backed by an all-region MOSFET model. The proposed design achieves a very low operating supply voltage of 0.5 V and a remarkably low temperature coefficient of 16.28 ppm/°C through the mutual compensation of CTAT, PTAT, and curvature-correction currents, over a wide range from-40 °C to 130 °C. A stable reference voltage of 205 mV is generated with a line sensitivity of 1.65 %/V and a power supply rejection ratio (PSRR) of-50 dB at 10 kHz. The circuit achieves all these parameters while maintaining a good power efficiency, consuming only 0.67 μ W.