A Standalone FPGA-based Miner for Lyra2REv2 Cryptocurrencies

arXiv:1905.08792 · cs.CR, eess.SP · Submitted 2019-05-21 · Read on arXiv

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Introduction to the show: ident: AI Radio. Generated commentary on the latest Artificial Intelligence papers.

Tom: Next we'll be talking about the paper "A Standalone FPGA-based Miner for Lyra2REv2 Cryptocurrencies".

Jane: The paper was written by Jean-François Tétu, Louis-Charles Trudeau, Michiel Van Beirendonck, Alexios Balatsoukas-Stimming and Pascal Giard from École de technologie supérieure (ETS) and imec-COSIC KU Leuven and Telecommunications Circuits Laboratory, École polytechnique fédérale de Lausanne (EPFL) and Department of Electrical Engineering, Eindhoven University of Technology.

Tom: Stay tuned as we take you through the paper and discuss its implications.

Paper discussion segment 1: Tom: We're looking at "A Standalone FPGA-based Miner for Lyra2REv2 Cryptocurrencies," and the title alone screams specialized hardware.

Jane: It's definitely focused, Tom, because they aren't just talking about general computing here. They are looking at a very specific type of math called Lyra2REv2 that is used to secure certain digital currencies.

Tom: Right, and the authors—Têtu, Trudeau, Van Beirendonck, Balatsoukas-Stimming, and Giard—come from some heavy-hitting institutions like ETS Montreal and KU Leuven.

Jane: They've brought together experts in hardware design and cryptography to tackle a problem that is actually quite practical for anyone interested in how these networks stay decentralized.

Lu: This research is fascinating because it's essentially about building a bespoke brain for a specific mathematical task! If you can design the logic gates to match the algorithm perfectly, you unlock incredible speeds.

Tom: Lu, do you think this level of specialization is what keeps these networks from being totally taken over by giant mining farms?

Lu: Exactly, because they are targeting "ASIC-resistant" algorithms. These are designed so that someone can't just build one massive, expensive machine to win everything; instead, you need smarter, more flexible hardware like the FPGAs they're using here.

Meng: I see where you're going with that, but from my side of things, I wonder about the barrier to entry for a regular person. The paper mentions that FPGAs are "readily available to the general public at reasonable prices," which is a huge deal for decentralization.

Jane: That's a great point, Meng. It’s like saying anyone can buy a high-end kitchen tool rather than needing an entire industrial factory to bake one specific kind of bread.

Meng: Precisely, and the authors are trying to prove that this "kitchen tool" approach is actually more efficient than using a standard graphics card or GPU. We'll see if their data backs up that claim in the next part.

Lalam: If we can make these specialized tools accessible, we're looking at a future where the power to validate transactions is distributed across many different types of hardware architectures. This diversity is what keeps digital ecosystems resilient and culturally inclusive by preventing any single entity from controlling the truth of the ledger.

Tom: That's a big vision, Lalam, but let's see how they actually built this thing in the next segment.

Paper discussion segment 2: Jane: Now that we know who is behind it, let's look at what they actually achieved with "A Standalone FPGA-based Miner for Lyra2REv2 Cryptocurrencies."

Tom: They didn't just make a small component; they built a whole standalone miner on an MPSoC, which is like a tiny computer system on a single chip.

Jane: To put that in simple terms, they took the complex "chain" of math—which includes things like Keccak and BLAKE2b—and mapped it directly onto the hardware's logic.

Tom: And the results are pretty wild: they hit a throughput of thirty-one point two five MHash/s.

Jane: But the real star is the energy efficiency, which they say is up to four point three times better than existing solutions and hits zero point eight zero µJ per hash.

Meng: That's a massive improvement in terms of operational costs, isn't it? If you're running a miner twenty-four/seven a four-fold increase in efficiency changes your entire business model.

Tom: It really does, Meng. They basically proved that they could beat both high-end GPUs and even existing FPGA miners by being more clever with how they used the chip's resources.

Meng: I'm looking at their use of the Xilinx MPSoC here; they used about eighty-five percent of the programmable logic, which is a very tight, efficient design. It’s not just fast; it’s densely packed to get every bit of value out of that silicon.

Lu: What's truly brilliant is how they handled the "wandering phase" of the algorithm! They used a memory matrix and specialized BRAM—Block RAM—to make sure the hardware doesn't sit around waiting for data.

Jane: It sounds like they turned a very messy, "wandering" math problem into a very orderly assembly line.

Lalam: This efficiency is what allows smaller communities to maintain their own networks without needing massive amounts of electricity. By reducing the energy barrier, you're essentially democratizing the ability to participate in secure digital economies.

Tom: It’s an impressive feat of engineering, but they also mention how this design can be tweaked for newer versions like Lyra2REv3.

Paper discussion segment 3: Tom: So we've seen the performance, but now we have to talk about the "future-proofing" aspect mentioned in "A Standalone FPGA-based Miner for Lyra2REv2 Cryptocurrencies."

Jane: Right, because the authors don't just stop at the current version; they explain how to modify their architecture for Lyra2REv3.

Tom: This is crucial because, as we know, developers often change these algorithms specifically to make old hardware obsolete.

Jane: They call the new version Lyra2MOD, and it adds a little twist where it picks certain bits from the internal state to decide which part of the memory to visit next.

Tom: It sounds like they're making the math even more "serial" or sequential, which is usually a nightmare for hardware designers.

Lu: That's exactly why it's a genius move! By making the algorithm depend on these "non-conventional" operations—like reading bits from the capacity part of a sponge—they make it much harder to build those specialized ASIC machines we were talking about earlier.

Meng: I was looking at their description of that change, and they mentioned it has a "negligible impact" on the resource requirements for their FPGA design. That's the holy grail for an engineer: adding more security for the network without making your hardware obsolete overnight.

Jane: It’s like building a car where you can upgrade the engine software to handle new types of fuel without having to rebuild the whole chassis.

Meng: Exactly, Jane, and that flexibility is what makes FPGAs so much more attractive than ASICs for these specific "ASIC-resistant" coins. You get the speed of custom hardware but with a safety net.

Lalam: This ability to adapt is vital for cultural stability in digital spaces; if the rules change, the tools can change too, preventing sudden collapses caused by massive shifts in mining power. It allows these digital societies to evolve gracefully rather than being disrupted by hardware monopolies.

Tom: It's a clever way to stay ahead of the curve, but we need to wrap this up and see what everyone thinks of the whole package.

Conclusion: Tom: We have covered a lot of ground on "A Standalone FPGA-based Miner for Lyra2REv2 Cryptocurrencies," from its specialized design to its incredible energy efficiency.

Jane: It really highlights how much work goes into making these decentralized systems actually work in the real world through smart hardware engineering.

Tom: Before we head out, let's get some final thoughts from the team. Lu, any parting shots?

Lu: I'm just incredibly excited about this level of hardware-algorithm co-design; it’s where the most creative engineering is happening right now!

Meng: From my side, the practical takeaway is clear: efficiency and flexibility are the two pillars that will decide which cryptocurrencies actually survive in the long run.

Lalam: And I see this as a fundamental step toward more inclusive digital infrastructures that can adapt to new challenges without centralizing power.

Tom: Well, thanks for joining us, everyone. We'll be back with another paper very soon!

Jane: See you next time!

Jean-François Tétu, Louis-Charles Trudeau, Michiel Van Beirendonck, Alexios Balatsoukas-Stimming, Pascal Giard

École de technologie supérieure (ETS) · imec-COSIC KU Leuven · Telecommunications Circuits Laboratory, École polytechnique fédérale de Lausanne (EPFL) · Department of Electrical Engineering, Eindhoven University of Technology

cs.CR, eess.SP

Submitted: 2019-05-21

Updated: 2020-01-29

Comments: 13 pages, accepted for publication in IEEE Trans. Circuits Syst. I. arXiv admin note: substantial text overlap with arXiv:1807.05764

Journal ref: IEEE Trans. Circuits Syst. I 67 (2020) 1194--1206

DOI: 10.1109/TCSI.2020.2970923

Code: https://github.com/Michielvb/lyra2-hw

License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/

Importance score: 90/100

The gist: This work presents "the first hardware implementation of the specific instance of Lyra2 that is used in Lyra2REv2" and "an FPGA-based hardware implementation of a standalone miner for Lyra2REv2 on a

Key concepts

FPGA: Field-Programmable Gate Array is a type of specialized hardware used to build custom circuits. In this research, it was used to map the complex mathematical algorithm directly onto the hardware logic for high-speed mining.
Lyra2REv2 Cryptocurrencies: This refers to a specific type of digital currency that uses a particular mathematical structure called Lyra2REv2 for its security. The paper focuses on creating specialized hardware to mine this specific type of cryptocurrency.
ASIC-resistant algorithms: These are mathematical algorithms designed so they cannot be easily replicated by single, massive mining farms. They require more flexible hardware like FPGAs instead of expensive, dedicated Application-Specific Integrated Circuits (ASICs).
Energy Efficiency: This measures how much energy is used to perform a task. The paper shows the miner achieves up to four point three times better efficiency than existing solutions, using only zero point eight zero microjoules per hash.

Terminology

Core — 48× in this paper · explained in 2 episodes
Programmable Logic — 11× in this paper
Verification — 11× in this paper · explained in 2 episodes
Energy Efficiency — 7× in this paper · explained in 3 episodes
Processing System — 5× in this paper
Blue Midnight Wish — 4× in this paper
Xilinx Multi-Processor System on Chip — 3× in this paper
George Mason University — 2× in this paper
Hybrid System — 1× in this paper · explained in 2 episodes

Summary

This work presents the first hardware implementation of the specific instance of Lyra2 that is used in Lyra2REv2 and an FPGA-based hardware implementation of a standalone miner for Lyra2REv2 on a Xilinx Multi-Processor System on Chip. The authors state that several properties of the aforementioned algorithm are exploited in order to optimize the design. The proposed miner is demonstrated to be significantly more energy efficient than both a GPU and a commercially available FPGA-based miner, specifically achieving "a hashing throughput of 31.25 MHash/s with an energy efficiency that is up to 4.3 times better than existing solutions at 0.80 µJ/Hash, while requiring approximately 85% of the programmable logic (PL) resources of the MPSoC. Additionally, the paper explains how the simplified Lyra and Lyra2REv2 architectures can be modified with minimal effort to also support the recent Lyra2REv3 chained hashing algorithm."

The technical implementation details include:

((

Architecture and Implementation:

The authors describe an MPSoC-based hardware architecture that implements the Lyra2REv2 miner, which can be easily modified to also implement a Lyra2REv3 miner. The computation-intensive part of the "chained hashing algorithm is implemented on the PL along with supporting logic, and use[s] the processing system (PS) capabilities of the MPSoC to run supporting software that is used to handle high-level cryptocurrency protocol tasks. To optimize throughput, the number of instances per hashing step in the chain [is] selected to maximize the overall mining algorithm throughput, resulting in a relatively balanced pipeline that is limited by the 31.25 MHash/s combined throughput of the Keccak and CubeHash cores."

Hardware Components:

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Lyra2 Core:

The implementation utilizes a pipelined architecture where dividing these sequential adders into eight pipeline stages greatly increases the achievable clock frequency. The design maps the memory matrix to a block RAM (BRAM) and uses standard true-dual-port BRAMs along with multipumping and replication techniques to provide necessary read/write ports.

Chained Hashing Components:

The miner implements a chain of algorithms including BLAKE, Keccak, CubeHash, Skein, Blue Midnight Wish (BMW), and Lyra2. The BLAKE architecture forms a 56-stage pipeline that concurrently processes 56 different message blocks, the Keccak implementation can then output one hash every 24 CCs, and the BMW implementation outputs one hash at every 2 CC.

System Integration:

The MPSoC implementation uses a flip-flop based register file for communication between the PS and PL, allowing the software to write 640-bit block headers, 256-bit target thresholds, and maximum nonces into the hardware. The hardware includes an input control finite-state machine (FSM) for nonce generation and a threshold-verification logic that uses a 256-bit comparator to determine whether the generated hash meets the threshold.

Performance Results:

The implementation was tested on a Xilinx ZCU102 Evaluation Kit, which is based on the Xilinx Zynq UltraScale+ 9EG (ZU9EG) MPSoC. The results show that "the proposed Lyra2REv2 FPGA-based miner has an estimated energy efficiency of 0.80 µJ/Hash at a throughput of 31.25 MHash/s, which is 4.3 and 2.1 times better than an NVIDIA Titan Xp GPU and a commercial FPGA-based miner, respectively."

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Improvements for AI systems

To improve AI systems using the principles found in this research, we should focus on hardware-software co-design specifically optimized for high-throughput, memory-intensive, and serial cryptographic operations.

Here are the specific improvements and the resulting capabilities:

Implement a Chained Pipeline Scheduler for Large Language Model (LLM) Inference

The paper describes a highly efficient method for balancing heterogeneous hashing cores with different execution times using specialized schedulers and asynchronous FIFOs.

The improved AI system would use this architecture to manage MoE (Mixture of Experts) models, where different sub-networks (experts) have varying computational latencies. The scheduler would dynamically balance data flow between fast shallow experts and slow deep experts, maximizing GPU/NPU utilization and preventing pipeline stalls during token generation.

Develop Hardware-Accelerated Memory-Wandering Attention Mechanisms

The paper introduces a highly optimized BRAM implementation for the Lyra2 algorithm, which relies on non-conventional memory access patterns (the wandering phase) to increase security/complexity.

The improved AI system would utilize dedicated, multi-ported on-chip memory architectures (using the paper's multipumping and replication techniques) to execute Sparse Attention or FlashAttention variants. This would allow the AI to perform extremely fast, non-linear memory lookups required for long-context window processing without the typical bottleneck of moving data between HBM (High Bandwidth Memory) and the compute cores.

Deploy Autonomous Edge-AI Miners/Validators via MPSoC Co-Design

The paper details a standalone miner that offloads high-level protocol tasks to an ARM Cortex-A53 (PS) while executing heavy computation on programmable logic (PL).

The improved AI system would be an autonomous, edge-deployed Validator Node for decentralized AI networks. It would use the MPSoC architecture to run complex consensus protocols and network communication in software while executing intensive cryptographic proof generation (for Zero-Knowledge Proofs or Verifiable Inference) in dedicated hardware logic, allowing for high-security AI verification on low-power, portable edge devices.

Implement Reduced-Round Cryptographic Verification for Secure AI Model Weights

The paper exploits the security of reduced-round permutations to increase throughput.

The improved AI system would use a similar reduced-round hardware implementation to perform ultra-fast integrity checks on model weights during runtime. This would protect against adversarial weight manipulation or bit-flip attacks in mission-critical AI deployments (like autonomous vehicles) by providing near-instantaneous verification of the model's mathematical state without significant latency penalties.